Full DTMF receiver Less than 35mW power consumption Industrial temperature range Uses quartz crystal or ceramic resonators Adjustable acquisition and release times 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin PLCCApplications
PABX Central office Mobile radio Remote control Remote data entry Call limiting Telephone answering systems Paging systems
Power down mode Inhibit mode Buffered OSC3 output (PLCC package only) CM8870C is fully compatible with CM8870 for 18-pin devices by grounding pin 5 and pin 6.
The CAMD CM8870/70C provides full DTMF receiver capability by integrating both the band-split filter and digital decoder functions into a single 18-pin DIP, SOIC, or 20-pin PLCC package. The CM8870/70C is manufactured using state-of-the-art CMOS process technology for low power consumption (35mW, MAX) and precise data handling. The filter section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The CM8870/70C decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code. This DTMF receiver minimizes external component count by providing an on-chip differential input amplifier, clock generator, and a latched three-state interface bus. The on-chip clock generator requires only a low cost TV crystal or ceramic resonator as an external component.
HIGH GROUP FILTER ZERO CROSSING DETECTORS LOW GROUP FILTER DIGITAL DETECTION ALGORITHM CODE CONVERTER AND LATCH� 2001 California Micro Devices Corp. All rights reserved.
This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. Notes: 1. Exceeding these ratings may cause permanent damage, functional operation under these conditions is not implied.
Symbol VDD Vdc IDD TA TS Parameter Power Supply Voltage SS ) Voltage on any Pin Current on any Pin Operating Temperature Storage Temperature 6V MAX 0.3V 10mA MAX � C ValueDC Characteristics: All voltages referenced to VSS, VDD to 85�C unless otherwise noted.
Symbol VDD IDD IDDQ PO VIL VIH IIH/LIL ISO RIN VTst VOL VOH IOL IOH VREF ROR Parameter Operating Supply Voltage Operating Supply Current Standby Supply Current Power Consumption Low Level Input Voltage High Level Input Voltage Input Leakage Current Pull Up (Source) Current on TOE Input Impedance, (IN+, IN�) Steering Threshold Voltage Low Level Output Voltage High Level Output Voltage Output Low (Sink) Current Output High (Source) Current Output Voltage Output Resistance VREF PD = VDD = 3.579 MHz; VDD = 5V VDD = 5V VDD = 5V VIN = VSS = VDD (Note 1) TOE = 0V, VDD @ 1KHz VDD = 5V VDD 5V, No Load VDD 5V, No Load VOUT = 0.4V VOUT = 4.6V VDD 5.0V, No Load Test Conditions MIN 4.75 TYP 3.0 MAX UNIT V k
Operating Characteristics: All voltages referenced to VSS, VDD to 85�C unless otherwise noted. Gain Setting Amplifier
Symbol IIN RIN VOS PSRR CMRR AVOL CL RL Vcm Parameter Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Common Mode Rejection DC Open Loop Voltage Gain Open Loop Unity Gain Bandwidth Output Voltage Swing Maximum Capacitive Load (GS) Maximum Resistive Load (GS) Common Mode Range (No Load) No Load SS 1 KHz (Note < 3V Test Conditions V DD MIN 10 �25 TYP MAX �100 UNIT mV dB MHz VP-P pF K VP-P�2001 California Micro Devices Corp. All rights reserved.
AC Characteristics: All voltages referenced to VSS, VDD to +85�C, fCLK = 3.579545 MHz using test circuit in Figure 1 unless otherwise noted.
Symbol Parameter Valid Input Signal Levels (each tone of composite signal) Positive Twist Accept Negative Twist Accept Freq. Deviation Aceept Limit Freq. Deviation Reject Limit Third Tone Tolerance Noise Tolerance Dial Tone Tolerance tDP tDA tREC tID tDO tPQ tPStD tQStD tPTE tPTD fCLK CLO
Notes: 1. dBm = decibels above or below a reference power of 1mW into a 600 load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40ms. Tone pause 40ms. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. Bandwidth limited to 3KHz) Gaussian Noise. 7. The precise dial tone frequencies are (350Hz and �2%. 8. For an error rate of better than 10,000 9. Referenced to lowest level frequency component in DTMF signal. 10. Minimum signal acceptance level is measured with specified maximum frequency deviation. 11. Input pins defined as IN+, IN�, and TOE. 12. External voltage source used to bias VREF. 13. This parameter also applies to a third tone injected onto the power supply. 14. Referenced to Figure 1. Input DTMF tone level �28dBm. 15. Times shown are obtained with circuit in Figure 1 (User adjustable).
Tone Present Detection Time Tone Absent Dectection Time MIN Tone Duration Accept MAX Tone Duration Reject MIN Interdigit Pause Accept MAX Interdigit Pause Reject Propagation Delay (St to Q) Propagation Delay (St to StD) Output Data Set (Q to StD) Propagation Delay (TOE to Q) Crystal/Clock Frequency Clock Ouput (OSC 2) Capacitive Load