D05022-152HC Datasheet

N-channel Fet Synchronous Buck Regulator Controller For Low Output Voltages


Features, Applications
LM2727/LM2737 N-Channel FET Synchronous Buck Regulator Controller for Low Output Voltages

The LM2727 and LM2737 are high-speed, synchronous, switching regulator controllers. They are intended to control currents to 20A with to 95% conversion efficiencies. The LM2727 employs output over-voltage and undervoltage latch-off. For applications where latch-off is not desired, the LM2737 can be used. Power up and down sequencing is achieved with the power-good flag, adjustable soft-start and output enable features. The LM2737 and LM2737 operate from a low-current 5V bias and can convert from to 16V power rail. Both parts utilize a fixedfrequency, voltage-mode, PWM control architecture and the switching frequency is adjustable from 2MHz by adjusting the value of an external resistor. Current limit is achieved by monitoring the voltage drop across the onresistance of the low-side MOSFET, which enhances low duty-cycle operation. The wide range of operating frequencies gives the power supply designer the flexibility to finetune component size, cost, noise and efficiency. The adaptive, non-overlapping MOSFET gate-drivers and high-side bootstrap structure helps to further maximize efficiency. The high-side power FET drain voltage can be from to 16V and the output voltage is adjustable down to 0.6V.


n Input power from 16V n Output voltage adjustable down 0.6V n Power Good flag, adjustable soft-start and output enable for easy power sequencing n Output over-voltage and under-voltage latch-off (LM2727) n Output over-voltage and under-voltage flag (LM2737) n Reference Accuracy: 125�C) n Current limit without sense resistor n Soft start n Switching frequency from 50 kHz to 2 MHz n TSSOP-14 package


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BOOT (Pin 1) - Supply rail for the N-channel MOSFET gate drive. The voltage should be at least one gate threshold above the regulator input voltage to properly turn on the high-side N-FET. LG (Pin 2) - Gate drive for the low-side N-channel MOSFET. This signal is interlocked with HG to avoid shoot-through problems. PGND (Pins 13) - Ground for FET drive circuitry. It should be connected to system ground. SGND (Pin 4) - Ground for signal level circuitry. It should be connected to system ground. VCC (Pin 5) - Supply rail for the controller. PWGD (Pin 6) - Power Good. This is an open drain output. The pin is pulled low when the chip is in UVP, OVP, or UVLO mode. During normal operation, this pin is connected to VCC or other voltage source through a pull-up resistor. ISEN (Pin 7) - Current limit threshold setting. This sources a fixed 50�A current. A resistor of appropriate value should be connected between this pin and the drain of the low-side FET.

EAO (Pin 8) - Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine the duty cycle. This pin is necessary for compensating the control loop. SS (Pin 9) - Soft start pin. A capacitor connected between this pin and ground sets the speed at which the output voltage ramps up. Larger capacitor value results in slower output voltage ramp but also lower inrush current. FB (Pin 10) - This is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating the control loop. FREQ (Pin 11) - The switching frequency is set by connecting a resistor between this pin and ground. SD (Pin - IC Logic Shutdown. When this pin is pulled low the chip turns off the high side switch and turns on the low side switch. While this pin is low, the IC will not start up. An internal 20�A pull-up connects this pin to VCC. HG (Pin 14) - Gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG to avoid shootthrough problems.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCC BOOTV Junction Temperature Storage Temperature Soldering Information Lead Temperature (soldering, to 150�C

Supply Voltage (VCC) Junction Temperature Range Thermal Resistance (JA) +125�C 155�C/W

VCC = 5V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA=TJ=+25�C. Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol Parameter Conditions VCC to +125�C VCC to +125�C VFB_ADJ FB Pin Voltage VCC to +125�C VCC to +125�C VCC to +125�C VCC to +125�C VON UVLO Thresholds Rising Falling = 0.55V Fsw = 0.65V Fsw 0V FB Voltage Going Up FB Voltage Going Down SS Voltage 0.8 0.15 Min Typ �s �A Max V Units

Shutdown VCC Current tPWGD1 tPWGD2 ISD ISS-ON PWGD Pin Response Time PWGD Pin Response Time SD Pin Internal Pull-up Current SS Pin Source Current

SS Pin Sink Current During Over SS Voltage = 2.5V Current ISEN Pin Source Current Trip Point Error Amplifier Unity Gain Bandwidth Error Amplifier DC Gain Error Amplifier Slew Rate FB Pin Bias Current EAO Pin Current Sourcing and Sinking Error Amplifier Maximum Swing = 0.65V VEAO = 0.55V VEAO = 0.65V Minimum Maximum to +125�C



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