D83SSeries Datasheet



Features, Applications

Description The D83S Series programmable amplifiers are digitally controlled gain modules that were designed for conditioning DC-coupled wide-band signals (AC coupled-optional). They are programmable from 6 dB steps with an 8-bit serial data stream for gain selection using clock, data and strobe inputs. Other standard performance features include differential input, single ended output, 5V interface logic, and low noise and distortion, making this plug-in ready-to-use amplifier ideal for many signal conditioning applications. Available options include AC coupled input and/or differential output. Features/Benefits:

Full power bandwidth to 100 kHz for wide dynamic range applications Compact 0.3" (32 pin DIP) size minimizes board space requirements Serial interface and software protocol allowing operation on a simple three wire bus. Data out line allows data verification and cascading of multiple amplifiers over the same serial interface. Plug-in ready-to-use, reducing engineering design and manufacturing time.

U.S. Selling Price (1-9) Orders for Export Minimum Order Value $150.00 Lead-Time: 3-4 weeks A.R.O
$240.00 each U.S. Selling Price + 20% F.O.B. Haverhill, MA Accept Visa, Mcard, Amex

Applications Data acquisition Test equipment Remote instrumentation systems Ground loop elimination in remote measurements Improvements in system dynamic range and resolution Telemetry Process control Digitally controlled auto ranging systems Medical, Scientific & engineering research Frequency Response

25 Locust St, Haverhill, Massachusetts 01830 Tel: 800/252-7074, 978/374-0761 FAX: 978/521-1839 e-mail: sales@freqdev.com Web Address: http://www.freqdev.com

The D83S programs via a three terminal serial data interface over a gain range from 1024 (~+60dB) using Clock (C), Strobe (S) and Data inputs (Di). A Data out (Do) connection is provided to permit cascading of multiple D83S's or "looping" of the input data to verify the programmed setting. Two stages of programmable gain/attenuation are used to optimize the D-C offset and gain bandwidth performance. The gain programming equation is: G=[1+3xD0+12xD1+48xD2+64xD3]x[1/4+(1/4)xD4+(1/2)xD5+D6]x[1+3xD7] where or "1" Note: the use of the compliments D1, D2 and C, S and Di Input Specifications Input Data Levels (Cmos/TTL Logic)

Input Voltage (Vd = 5Vdc) Low Level In High Level In Input Current Low Level In High Level In Input Capacitance 0 Vdc min., 3.5 Vdc min., 1.5 Vdc max. 5.0 Vdc max.

-10-5 �A typ., -1 �A max. +10-5 �A typ., +1 �A max. 5 pF typ., 7.5 pF max.

Recommended Programming Table All combinations of programming inputs produce valid gain settings as determined by the gain equation but can result in unusual values of gain. To minimize the multiplication of D-C offset and to maximize the bandwidth at high gains the following is the recommended programming format for binary weighted gains from 1024 (~60dB). Gain ( V/V )

Programming Sequence The programming input circuit a CD4094 series 8 bit shift register with latches. It requires an 8 bit input serial data stream, D7), a clock C to shift and a strobe S to latch the data (see note 1). A timing sequence must be observed to insure accurate shifting and latching of the input data. The input data bits, D0 through D7 are entered in reverse order, i.e. the MSB, D7, is the first bit to be entered followed by D6 etc. and ending with the LSB, D0 (refer to timing diagram).

The Clock shifts the input data Di through the shift registers when it transitions from low to high. For the input data to be accurately received, it must have been present for at least Ts at the time of the rising clock transition. The maximum clock pulse frequency is 1.25MHz. Data from the shift registers propagates through the latches when the strobe is high. Data is latched when the Strobe transitions from high to low. To retain a programmed setting it is necessary to hold the strobe low (or to shut off the clock). Keeping the strobe low will allow the clock to shift a new set of input data into the registers without changing the latched setting. To latch a new set of data the strobe must be set to its high state, after the last bit of the new input word (D0) has been shifted in (>Tcs), held high for a minimum time of Tsw and then returned to its low state to latch and hold the setting. The return S to its low state must occur before the rise of the clock that accepts the D7 of the next data word (Tsc>0). Timing Diagram

D7 Valid Input D6 Valid Input D0 Valid Input Tcs D7 Valid Input Tsc

Notes: 1.) Data is shifted into register on positive edge of clock. 2.) Data is latched on negative edge of strobe. Ts is set up time (valid data before clock). 4.) Tcs is time between D0 clock and start of strobe. 5.) Tsw is strobe width. 6.) Tsc is time between strobe end and D7 clock (next word). 7.) Tcw is clock width. Th is hold time (Valid data after clock rising edge).

Minimum Setup Times Time data must be present before rise of clock pulse. Time from rise of Clock for last data bit, D0, to rise of Strobe pulse. Strobe width. Time from fall of Strobe to rise of next Clock pulse. Clock pulse width. Maximum Clock pulse frequency. Time data must be valid after rise of clock pulse.

Note 1: The C, P and Di inputs are Tri-state C-MOS logic. They contain protection circuitry to guard against damage due to high static voltages or electric fields, however the application of any voltages higher than the +5V or lower than the 0V supply voltages can cause permanent damage. These inputs must always be connected to an appropriate logic voltage level. Permanent damage can also result C, P and Di are allowed to float unconnected. If the D83S is used in a configuration where these inputs can become disconnected from their drive circuits, or if their drive circuits are not powered by the same +5V source, it is recommended to use 10k pull up resistors +5V on these inputs.



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