HomedatasheetD950CORE

D950CORE Datasheet

16 Bit Fixed Point Digital Signal Processor Core
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Features, Applications
16-Bit Fixed Point Digital Signal Processor (DSP) Core

Peripherals and Memory s Macrocells for peripherals such as the bus switch unit, interrupt controller and DMA controller s Standard cells library, I/O library s Memory generators for RAM and ROM Development Tools s JTAG PC board with graphic windowed high level source debugger for AS-DSP emulation s Complete crash-barrier chain (assembler / simulator / linker) running on PC and SUN, s Complete GNU chain (assembler / simulator / linker / C compiler / C debugger) for SUN s VHDL model (SYNOPSYS & MENTOR)

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice

Performance s 66 Mips - 15ns instruction cycle time Memory Organization s HARVARD architecture s Two x 16-bit data memory spaces s One x 16-bit program memory space s 2 stacks in data memory spaces Fast and Flexible Buses s Two 16-bit address 16-bit data nonmultiplexed data buses s One 16-bit address 16-bit data nonmultiplexed instruction bus Data Calculation Unit x 16-bit parallel multiplier s 40-bit barrel shifter unit s 40-bit ALU s Two 40-bit extended precision accumulators s Fractional and integer arithmetic with support for floating point and multi-precision s 16-bit bit manipulation unit (BMU) Address Calculation Unit s Two address calculation units with modulo and bit-reverse capability x 16-bit address registers x 16-bit index registers x 16-bit base and maximum address registers for modulo addressing Program Control Unit s 16-bit program counter s 3 Hardware Loop Capabilities Power Consumption s Single 3.3V power supply s Low-power standby mode Electrical Characteristics s Operating frequency down to DC Channels s General purpose 8-bit I/O port s Dedicated hardware for Emulation and Test, IEEE 1149.1 (JTAG) interface compatible

INTRODUCTION. 5 PIN DESCRIPTION. 6 FUNCTIONAL OVERVIEW. 11 BLOCK DESCRIPTION. 13 4.1 DATA CALCULATION UNIT (DCU). Introduction. 13 Registers. 14 Multiplier. 15 Barrel Shifter Unit (BSU). 16 Arithmetic and Logic Unit (ALU). 17 Bit Manipulation Unit (BMU). 18 Introduction. 20 Registers. 21 Addressing modes. 21 Introduction. 25 Registers. 26 Instruction pipeline. 26 Interrupt Sources. 26 Loop Controller. 28 Sequence control. 29 Halting program execution. 29 Memory Moves with Wait States. 31 Introduction. 32 Registers. 33 STA: Status register. 34 CCR: Condition Code Register. 36

SOFTWARE ARCHITECTURE. 40 5.1 INTRODUCTION. 40 5.2 REGISTER LIST. 41 5.3 CONDITION LIST. 41

5.4 INSTRUCTION SET. Assignment Instructions. 43 ALU Instructions. 45 Bit Manipulation Instructions. 50 Program Control Instructions. 51 Conditional Assignment Instruction. 52 Loop Control Instructions. 52 Co-processor Instructions. 53 Stack Instructions. 54

5.5 INSTRUCTION CYCLE AND WORD COUNT. 55 ELECTRICAL SPECIFICATIONS. 6.1 DC ABSOLUTE MAXIMUM RATINGS. 6.2 DC ELECTRICAL CHARACTERISTICS (CORE LEVEL). 6.3 AC CHARACTERISTICS. Bus AC Electrical Characterstics (for X, Y and I buses). 57 Control I/O Electrical Characteristics. 58 Hardware Reset. 59 Wait States. 60 Interrupt. 62 HOLD. 63 JUMP on Port Condition. 65

ANNEX - HARDWARE PERIPHERAL LIBRARY. 66 7.1 CO-PROCESSOR. 66 7.2 BUS SWITCH UNIT (BSU). Introduction. 67 I/O interface. 68 Operation. 69 BSU control registers. 70 Introduction. 72 I/O interface. 73 Interrupt Controller Peripheral Registers. 73 Introduction. 77


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