HomedatasheetDA28F640J5-150

DA28F640J5-150 Datasheet

Strataflash Memory Technology 32 And 64 Mbit
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High-Density Symmetrically-Blocked Architecture 64 128-Kbyte Erase Blocks 32 128-Kbyte Erase Blocks 5 V VCC Operation 2.7 V I/O Capable Configurable or x16 I/O 120 ns Read Access Time 150 ns Read Access Time (64 M) Enhanced Data Protection Features Absolute Protection with VPEN = GND Flexible Block Locking Block Erase/Program Lockout during Power Transitions Industry-Standard Packaging �BGA* Package, SSOP and TSOP Packages (32 M)

Cross-Compatible Command Support Intel Basic Command Set Common Flash Interface Scaleable Command Set 32-Byte Write Buffer 6 �s per Byte Effective Programming Time 640,000 Total Erase Cycles M) 320,000 Total Erase Cycles M) 10,000 Erase Cycles per Block Automation Suspend Options Block Erase Suspend to Read Block Erase Suspend to Program System Performance Enhancements STS Status Output Intel StrataFlashTM Memory Flash Technology

Capitalizing on two-bit-per-cell technology, Intel StrataFlashTM memory products provide 2X the bits in 1X the space. Offered 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market. Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOXTM technology as Intel's one-bit-per-cell products, Intel StrataFlash memory devices take advantage of 400 million units of manufacturing experience since As a result, Intel StrataFlash components are ideal for code or data applications where high density and low cost are required. Examples include networking, telecommunications, audio recording, and digital imaging. By applying FlashFileTM memory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5 and 28F320S5). Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel's 0.4 micron ETOXTM V process technology, Intel StrataFlash memory provides the highest levels of quality and reliability.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F320J5 and 28F640J4 may contain design defects or errors known as errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, 80217-9808 or call 1-800-548-4725 or visit Intel's website at http://www.intel.com

*Third-party brands and names are the property of their respective owners.

PAGE 5.0 DESIGN CONSIDERATIONS........................40 5.1 Three-Line Output Control..........................40 5.2 STS and Block Erase, Program, and LockBit Configuration Polling............................40 5.3 Power Supply Decoupling..........................40 5.4 VCC, VPEN, RP# Transitions........................40 5.5 Power-Up/Down Protection........................41 5.6 Power Dissipation.......................................41 6.0 ELECTRICAL SPECIFICATIONS..................42 6.1 Absolute Maximum Ratings........................42 6.2 Operating 6.5 AC Characteristics-- Read-Only 6.6 AC Characteristics-- Write Operations.......48 6.7 Block Erase, Program, and Lock-Bit Configuration Performance........................51 7.0 ORDERING INFORMATION.........................52 8.0 ADDITIONAL INFORMATION......................53

1.0 PRODUCT OVERVIEW...................................5 2.0 PRINCIPLES OPERATION.....................11 2.1 Data Protection..........................................12 3.0 BUS Read..........................................................13 3.2 Output Reset/Power-Down....................................13 3.5 Read Query................................................14 3.6 Read Identifier Write..........................................................14 4.0 COMMAND DEFINITIONS............................14 4.1 Read Array Command................................18 4.2 Read Query Mode Command.....................18 4.2.1 Query Structure Output.......................18 4.2.2 Query Structure Overview...................20 4.2.3 Block Status Register..........................21 4.2.4 CFI Query Identification String.............22 4.2.5 System Interface Information...............23 4.2.6 Device Geometry Definition.................24 4.2.7 Primary-Vendor Specific Extended Query Table.......................................25 4.3 Read Identifier Codes Command...............26 4.4 Read Status Register Command................27 4.5 Clear Status Register Command................27 4.6 Block Erase Command..............................27 4.7 Block Erase Suspend Command................27 4.8 Write to Buffer Command...........................28 4.9 Byte/Word Program Commands.................28 4.10 Configuration Command...........................29 4.11 Set Block and Master Lock-Bit Commands................................................29 4.12 Clear Block Lock-Bits Command..............30


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