HomedatasheetDAC1007

DAC1007 Datasheet

Microprocessor Compatible, Double Buffered D/A Converter (obsolete)
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Description

Features, Applications

The DAC1006/7/8 are advanced CMOS/Si-Cr 10-, 9- and 8-bit accurate multiplying DACs which are designed to interface directly with the 8085, Z-80 and other popular microprocessors. These DACs appear as a memory location or an I/O port to the �P and no interfacing logic is needed. These devices, combined with an external amplifier and voltage reference, can be used as standard D/A converters; and they are very attractive for multiplying applications (such as digitally controlled gain blocks) since their linearity error is essentially independent of the voltage reference. They become equally attractive in audio signal processing equipment as audio gain controls or as programmable attenuators which marry high quality audio signal processing to digitally based systems under microprocessor control. All of these DACs are double buffered. They can load all 10 bits or two 8-bit bytes and the data format is left justified. The analog section of these DACs is essentially the same as that of the DAC1020. The DAC1006 series are the 10-bit members of a family of microprocessor-compatible DAC's (MICRO-DAC'sTM). For applications requiring other resolutions, the DAC0830 series (8 bits) and the DAC1208 and DAC1230 (12 bits) are available alternatives. Part DAC1007 DAC1008 Accuracy (bits) For leftjustified data Pin Description

Features

n Uses easy to adjust END POINT specs, NOT BEST STRAIGHT LINE FIT n Low power consumption n Direct interface to all popular microprocessors n Integrated thin film on CMOS structure n Double-buffered, single-buffered or flow through digital data inputs n Loads two 8-bit bytes or a single 10-bit word n Logic inputs which meet TTL voltage level specs (1.4V logic threshold) n Works with � 10V reference full 4-quadrant multiplication n Operates STAND ALONE (without �P) if desired n Available in 0.3" standard 20-pin package n Differential non-linearity selection available as special order

Output Current Settling Time: 500 ns Resolution: 10 bits Linearity: 10, 9, and 8 bits (guaranteed over temp.) Gain Tempco: -0.0003% of FS/�C Low Power Dissipation: 20 mW (including ladder) Single Power Supply: to 15 VDC

MICRO-DACTM and BI-FETTM are trademarks of National Semiconductor Corp.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Digital Input Voltage at VREF Input Storage Temperature Range Package Dissipation = 25�C (Note 3) DC Voltage Applied or IOUT2 (Note 4) 17 VDC VCC to GND mV to VCC

ESD Susceptibility (Note 11) Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic)

Temperature Range Part numbers with "LCN" and "LCWN" suffix Voltage at Any Digital Input

Tested at VCC = 4.75 VDC and 15.75 VDC, = 25�C, VREF = 10.000 VDC unless otherwise noted Parameter Resolution Linearity Error Endpoint adjust only TMIN TA < TMAX DAC1007 DAC1008 Differential Nonlinearity Endpoint adjust only TMIN TA < TMAX DAC1007 DAC1008 Monotonicity TMIN TA < TMAX DAC1007 DAC1008 Gain Error Gain Error Tempco Power Supply Rejection Using internal Rfb -10VVREF+10V TMIN TA < TMAX Using internal Rfb All digital inputs latched high VCC to 5.25V Reference Input Resistance Output Feedthrough Error VREF = 100 kHz All data inputs latched low 90 mVp-p k FSR/V % FSR/V % FSR/V of FS/�C bits of FSR % of FSR % of FSR of FSR % of FSR % of FSR Conditions See Note Min. VCC � 5% Typ. Max. 10 Min. Typ. Max. 10 bits VCC � 5% Units

Tested at VCC = 4.75 VDC and 15.75 VDC, = 25�C, VREF = 10.000 VDC unless otherwise noted Parameter Output IOUT1 IOUT2 Supply Current Drain Output Leakage Current IOUT1 IOUT2 Digital Input Voltages Conditions All data inputs latched low All data inputs latched high TMINTATMAX All data inputs latched low All data inputs latched high TMINTATMAX Low level LCN and LCWM suffix High level (all parts) Digital Input Currents Current Settling Time Write and XFER Pulse Width Data Set Up Time Data Hold Time Control Set Up Time Control Hold Time tCH tCS tDH tDS tW VIL = 0V, VIH = 25�C TMINTATMAX VIL = 0V, VIH = 25�C TMINTATMAX VIL = OV, VIH = 25�C TMINTATMAX VIL = 0V, VIL = 25�C TMINTATMAX VIL = 0V, VIH = 25�C TMINTATMAX ns tS TMINTATMAX Digital inputs < 0.8V Digital inputs > 2.0V VIL = 0V, VIH = 5V �ADC ns VDC nA 6 See Note Min. Capacitance IOUT2 VCC � 5% Typ. Max. Min. Typ. Max. pF mA VCC � 5% Units

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking. Note 4: For current switching applications, both IOUT1 and IOUT2 must go to ground or the "Virtual Ground" of an operational amplifier. The linearity error is degraded by approximately VOS�VREF. For example, if VREF = 10V then 1 mV offset, VOS, or IOUT2 will introduce an additional 0.01% linearity error. Note 5: Guaranteed at VREF � 10 VDC and VREF � 1 VDC. Note 6: TMIN = 0�C and TMAX = 70�C for "LCN" and "LCWM" suffix parts. Note 7: The unit "FSR" stands for "Full Scale Range." "Linearity Error" and "Power Supply Rejection" specs are based on this unit to eliminate dependence on a particular VREF value and to indicate the true performance of the part. The "Linearity Error" specification of the "0.05% of FSR (MAX)." This guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within of a straight line which passes through zero and full scale. Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tW) of 320 ns. A typical part will operate with tW of only 100 ns. The entire write pulse must occur within the valid data interval for the specified tW, tDS, tDH, and tS to apply. Note 9: Guaranteed by design but not tested.


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