HomedatasheetDAC1219LCJ

DAC1219LCJ Datasheet

12-bit Binary Multiplying D/A Converter
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Description

Features, Applications

The DAC1218 and the DAC1219 are 12-bit binary 4-quadrant multiplying to A converters The linearity differential non-linearity and monotonicity specifications for these converters are all guaranteed over temperature In addition these parameters are specified with standard zero and fullscale adjustment procedures as opposed to the impractical best fit straight line guarantee This level of precision is achieved though the use of an advanced silicon-chromium (SiCr) R-2R resistor ladder network This type of thin-film resistor eliminates the parasitic diode problems associated with diffused resistors and allows the applied reference voltage to range from to 25V independent of the logic supply voltage CMOS current switches and drive circuitry are used to achieve low power consumption (20 mW typical) and minimize output leakage current errors (10 nA maximum) Unique digital input circuitry maintains TTL compatible input threshold voltages over the full operating supply voltage range The DAC1218 and DAC1219 are direct replacements for the AD7541 series AD7521 series and AD7531 series with a significant improvement in the linearity specification In applications where direct interface of the to A converter to a microprocessor bus is desirable the DAC1208 and DAC1230 series eliminate the need for additional interface logic

Features

Linearity specified with zero and full-scale adjust only Logic inputs which meet TTL voltage level specs (1 4V logic threshold) Works with g 10V reference full 4-quadrant multiplication All parts guaranteed 12-bit monotonic

Current Settling Time Resolution Linearity (Guaranteed over temperature) Gain Tempco Low Power Dissipation Single Power Supply

where 1 if digital input is high 0 if digital input is low
BI-FETTM is a trademark of National Semiconductor Corp C1995 National Semiconductor Corporation

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) Voltage at Any Digital Input Voltage at VREF Input Storage Temperature Range DC Voltage Applied or IOUT2 (Note 4) Lead Temp (Soldering 10 seconds) ESD Susceptibility (Note 11) 17 VDC VCC to GND g 25V

Temperature Range DAC1219LCJ DAC1218LCJ-1 Range of VCC Voltage at Any Digital Input TMIN TA s TMAX

VREF 10 000 VDC VCC 11 4 VDC 15 75 VDC unless otherwise noted Boldface limits apply from TMIN to TMAX (see Note 9) all other limits 25 C Parameter Resolution Linearity Error (End Point Linearity) Zero and Full-Scale Adjusted DAC1218 DAC1219 Zero and Full-Scale Adjusted 5 9

Monotonicity Gain Error (Min) Gain Error (Max) Gain Error Tempco Power Supply Rejection Reference Input Resistance All Digital Inputs High (Min) (Max) Output Feedthrough Error Output Capacitance VREF e 120 Vp-p e 100 kHz All Data Inputs Low All Data Inputs IOUT1 High IOUT2 All Data Inputs IOUT1 Low IOUT2 Using Internal RFb VREF g 1V

Supply Current Drain Output Leakage Current IOUT1 IOUT2 Digital Input Threshold Digital Input Currents ts Current Settling Time All Data Inputs Low All Data Inputs High Low Threshold High Threshold Digital Inputs k0 8V Digital Inputs e 100X Output Settled 0 01% All Digital Inputs Switched Simultaneously

Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking Note 4 Both IOUT1 and IOUT2 must go to ground or the virtual ground of an operational amplifier The linearity error is degraded by approximately VOS d VREF For example if VREF e 10V then 1 mV offset VOS or IOUT2 will introduce an additional 0 01% linearity error Note 5 The unit FSR stands for full-scale range Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular VREF value to indicate the true performance of the part The Linearity Error specification of the 012% of FSR This guarantees that after performing a zero and full-scale adjustment the plot of the 4096 analog voltage outputs will each be within 012% c VREF of a straight line which passes through zero and fullscale The unit ppm of FSR (parts per million of full-scale range) and ppm of FS (parts per million of full-scale) are used for convenience to define specs of very small percentage values typical of higher accuracy converters 1 ppm of FSR e VREF 106 is the conversion factor to provide an actual output voltage quantity For example the gain error tempco spec g 6 ppm FS C represents a worst-case full-scale gain error change with temperature from 75 (10b3) VREF which 075% of VREF Note 6 To achieve this low feedthrough in the D package the user must ground the metal lid If the lid is left floating the feedthrough is typically 6 mV Note 10 nA leakage current with RFb e 20k and VREF e 10V corresponds to a zero error of FS Note 8 Human body model 100 pF discharged through 5 kX resistor Note 9 Tested limit for b 1 suffix parts applies only 25 C Note 10 Typicals are 25 C and represent the most likely parametric norm Note 11 Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level) Note 12 Design limits are guaranteed but not 100% production tested These limits are not used to calculate outgoing quality levels

Digital Input Threshold vs VCC Digital Input Threshold vs Temperature
Gain and Linearity Error Variation vs Supply Voltage

Features

Parameters

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Manufacturer information

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