DAC1243X_AL Datasheet

Mixed Signal Cores->0.25um


Features, Applications

This core is a CMOS hexa-channel 10bit D/A converter for general & video. The DAC1243X-AL core is in the Samsung 0.25um 2.5V process. Digital inputs are coded as binary. Each DAC channel includes power down control and the ability sense output load. An external(optional) or 0.7V reference voltage (VBIAS) and a external resister define the full-scale current together. It uses the two of current-segment and -weighted.


Maximum conversion rate 40MSPS +2.5V CMOS monolithic construction �0.75LSB differential linearity (typical) �1.0LSB integral linearity (typical) External or internal voltage reference (Including Band Gap Reference Block) Hexa Channel DAC 10-Bit parallel Straight Binary Digital input per channel DAC auto-load detection circuitry Temperature: ~ 70�C Each channel Power_Down


High Definition Television(HDTV) High Resolution Color Graphics Hard Disk Driver (HDD) CAE/CAD/CAM Image Processing Instrumentation

IO3 IO4 Segmented MSBs Digital Decode Binary Weighted LSBs Segmented MSBs Digital Decode Binary Weighted LSBs Segmented MSBs Digital Decode Binary Weighted LSBs IO5 IO6 Segmented MSBs Binary Weighted LSBs Segmented MSBs Binary Weighted LSBs Segmented MSBs Binary Weighted LSBs Digital Decode Digital Decode Digital Decode

CLK DTOUT PRE SEL<2:0> ALLPD Bias_ gen Auto-load Detect CCOMP VBIAS IREF

Ver 1.3 (Aug. 2000) This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice.

Name PDAC[5:0] CLK PRE I/O Type DI I/O Pad piar50_abb picc_abb piar50_abb Pin Description Individual DAC power down control. When activated (high), the corresponding DAC is disabled. DAC master clock. Input data is sampled with the rising edge of CLK. Control strobe for the DAC auto-load detection comparator. When PRE transitions high-to-low, the auto-load detect circuit evaluates its selected input. Appropriate settling time must be allowed before the comparator output (DTOUT) is used. When not used, PRE should be left high. 10-bit straight binary digital input for each DAC channel.

Power down control for Bandgap and all six DACs. A high level disables all six DACs plus the bandgap reference regardless of the states of PDAC0-5 Comparator output for detection of resistive load at DAC output. A low at the detect output indicates that the output voltage of the selected channel is above 0.53V and therefore that no load is attached. Internal DAC compensation node. Connect external 0.1uF cap to VDD25AA1. External resistor from this node to VSS25AA1 defines the full scale output current for the DACs. External reference voltage output.

I/O TYPE ABBR. AI: Analog Input DI: Digital Input AO: Analog Output DO: Digital Output AB: Analog Bidirectional DB: Digital Bidirectional AP: Analog Power DP: Digital Power AG: Analog Ground DG: Digital Ground



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