HomedatasheetDAC2900Y/2K

DAC2900Y/2K Datasheet

ti DAC2900, Dual, 10-Bit, 125Msps Digital-to-analog Converter
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Description

Features, Applications

FEATURES

q 125MSPS UPDATE RATE q SINGLE SUPPLY: +5V q HIGH SFDR: 68dB at fOUT 20MHz q LOW GLITCH: 2pVs q LOW POWER: +5V q INTERNAL REFERENCE q POWER-DOWN MODE: 23mW

APPLICATIONS

q COMMUNICATIONS: Base Stations, WLL, WLAN Baseband I/Q Modulation q MEDICAL/TEST INSTRUMENTATION q ARBITRARY WAVEFORM GENERATORS (ARB) q DIRECT DIGITAL SYNTHESIS (DDS)

DESCRIPTION

The is a monolithic, 10-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is optimized to provide high dynamic performance while dissipating only a +5V single supply. Operating with high update rates to 125MSPS, the DAC2900 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suitable for "Direct IF" applications. The DAC2900 has been optimized for communications applications in which separate I and Q data are processed while maintaining tight gainand offset matching. Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output configurations.

The DAC2900 combines high dynamic performance with a high throughput rate to create a cost-effective solution for a wide variety of waveform-synthesis applications: Pin compatibility between family members provides 12-bit (DAC2902), and 14-bit (DAC2904) resolution. Pin compatible to the AD9763 dual DAC. Gain matching is typically 0.5% of full-scale, and offset matching is specified at 0.02% max. The DAC2900 utilizes an advanced CMOS process; the segmented architecture minimizes output-glitch energy, and maximizes the dynamic performance. All digital inputs are +3.3V and +5V logic compatible. The DAC2900 has an internal reference circuit, and allows use of an external reference. The DAC2900 is available a TQFP-48 package, and is specified over the extended industrial temperature range to +85�C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

+VA to AGND........................................................................ to +6V +VD to DGND........................................................................ to +6V AGND to DGND................................................................. to �0.3V +VA to +VD............................................................................... to +6V CLK, PD to DGND..................................................... D0-D9 to DGND......................................................... + 0.3V IOUT, IOUT to AGND........................................................ + 0.3V BW, BYP to AGND..................................................... + 0.3V REFIN, FSA to AGND................................................. + 0.3V INT/EXT to AGND...................................................... + 0.3V Junction Temperature.................................................................... +150�C Case Temperature......................................................................... +100�C Storage Temperature.................................................................... +125�C

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE DRAWING NUMBER 355 PACKAGE DESIGNATOR 48-PDF SPECIFIED TEMPERATURE RANGE to +85�C PACKAGE MARKING DAC2900Y ORDERING DAC2900Y/250 DAC2900Y/2K TRANSPORT MEDIA Tape and Reel Tape and Reel

NOTE: (1) Models with a slash are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "DAC2900Y/2K" will get a single 2000-piece Tape and Reel. PRODUCT DAC2900 EVM ORDERING NUMBER DAC2900-EVM COMMENT Fully populated evaluation board. See user manual for details.

TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, 50� doubly-terminated, unless otherwise noted. Independant Gain Mode. DAC2900Y PARAMETER RESOLUTION Output Update Rate (fCLOCK) STATIC ACCURACY(1) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) DYNAMIC PERFORMANCE Spurious-Free Dynamic Range (SFDR) fOUT = 1MHz, fCLOCK = +25�C TMIN to TMAX = +25�C TMIN to TMAX To Nyquist 0dBFS Output �6dBFS Output �12dBFS Output CONDITIONS MIN TYP MAX UNITS Bits MSPS LSB

fOUT = 1MHz, fCLOCK = 26MSPS fOUT = 2.18MHz, fCLOCK = 52MSPS fOUT = 5.24MHz, fCLOCK = 52MSPS fOUT = 10.4MHz, fCLOCK = 78MSPS fOUT = 15.7MHz, fCLOCK = 78MSPS fOUT = 5.04MHz, fCLOCK = 100MSPS fOUT = 20.2MHz, fCLOCK = 100MSPS fOUT = 20.1MHz, fCLOCK = 125MSPS fOUT = 40.2MHz, fCLOCK = 125MSPS Spurious-Free Dynamic Range within a Window fOUT = 1.0MHz, fCLOCK = 50MSPS fOUT = 5.02MHz, fCLOCK = 50MSPS fOUT = 5.03MHz, fCLOCK = 78MSPS fOUT = 5.04MHz, fCLOCK = 125MSPS Total Harmonic Distortion (THD) fOUT = 1MHz, fCLOCK = 50MSPS fOUT = 5.02MHz, fCLOCK = 50MSPS fOUT = 5.03MHz, fCLOCK = 78MSPS fOUT = 5.04MHz, fCLOCK = 125MSPS Multitone Power Ratio fOUT to 2.99MHz, fCLOCK = 65MSPS

TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, 50� doubly terminated, unless otherwise noted. Independant Gain Mode. DAC2900Y PARAMETER DYNAMIC PERFORMANCE (Cont.) Signal-to-Noise Ratio (SNR) fOUT = 5.02MHz, fCLOCK = 50MHz Signal-to-Noise and Distortion (SINAD) fOUT = 5.02MHz, fCLOCK = 50MHz Channel Isolation fOUT = 1MHz, fCLOCK = 52MSPS fOUT = 20MHz, fCLOCK = 125MSPS Output Settling Time(2) Output Rise Time(2) Output Fall Time(2) Glitch Impulse DC ACCURACY Full-Scale Output Range(3)(FSR) Output Compliance Range Gain Error--Full-Scale Gain Error Gain Matching Gain Drift Offset Error Offset Drift Power-Supply Rejection, +VA Power-Supply Rejection, +VD Output Noise Output Resistance Output Capacitance REFERENCE/CONTROL AMP Reference Voltage Reference Voltage Drift Reference Output Current Reference Multiplying Bandwidth Input Compliance Range DIGITAL INPUTS Logic Coding Logic High Voltage, VIH Logic Low Voltage, VIL Logic High Voltage, VIH Logic Low Voltage, VIL Logic High Current, IIH(4) Logic Low Current Input Capacitance POWER SUPPLY Supply Voltages +VA +VD Supply Current IVD(5) IVD(6) Power Dissipation(5) Power Dissipation(6) Power Dissipation(5) Power Dissipation Thermal Resistance, JA JC TEMPERATURE RANGE Specified Operating CONDITIONS 0dBFS Output 0dBFS Output MIN TYP 62 61.5 MAX UNITS dBc

dBc ns pV-s mA V %FSR ppmFSR/�C %FSR ppmFSR/�C %FSR/V pA/ Hz pA/sHz pF V ppmFSR/�C nA MHz V

All Bits HIGH, IOUT With Internal Reference With External Reference With Internal Reference With Internal Reference With Internal Reference With Internal Reference +3.3V, �10% IOUT = 20mA, RLOAD = 50 IOUT = 2mA IOUT, IOUT to Ground

NOTES: (1) At output lOUT, while driving a virtual ground. (2) Measured single-ended into 50� load. (3) Nominal full-scale output current is 32 IREF; see Application section for details. (4) Typically 45�A for the PD pin, which has an internal pull-down resistor. (5) Measured at fCLOCK = 25MSPS and fOUT 1MHz. (6) Measured at fCLOCK = 100MSPS and fOUT = 40MHz.


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