12-Bit Dual Transmit DAC 200 MSPS Update Rate Single Supply: 3.6 V High SFDR: 85 dBc at 5 MHz High IMD3: 78 dBc at 15.1 and 16.1 MHz WCDMA ACLR: at 30.72 MHz Independent or Single Resistor Gain Control Dual or Interleaved Data On-Chip 1.2-V Reference Low Power: 330 mW Power-Down Mode: 15 mW Package: 48-Pin TQFPAPPLICATIONS
Cellular Base Transceiver Station Transmit Channel � CDMA: W-CDMA, IS-95 � TDMA: GSM, IS-136, EDGE/UWC-136 Medical/Test Instrumentation Arbitrary Waveform Generators (ARB) Direct Digital Synthesis (DDS) Cable Modem Termination System (CMTS)IOUTB1 DB[11:0] MODE GSET 1.2 V Reference SLEEP EXTIO Latch B 12-b DAC IOUTB2 BIASJ_B
The is a monolithic, dual-channel 12-bit high-speed digital-to-analog converter (DAC) with on-chip voltage reference. Operating with update rates to 200 MSPS, the DAC5662 offers exceptional dynamic performance and tight-gain and offset matching, characteristics that make it suitable in either I/Q baseband or direct IF communication applications. Each DAC has a high-impedance differential current output, suitable for single-ended or differential analog-output configurations. External resistors allow scaling the full-scale output current for each DAC separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used. The DAC5662 has two 12-bit parallel input ports with separate clocks and data latches. For flexibility, the DAC5662 also supports multiplexed data for each DAC on one port when operating in the interleaved mode. The DAC5662 has been specifically designed for a differential transformer coupled output with a 50- doubly terminated load. For a 20-mA full-scale output current a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (-2 dBm output power) are supported.
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PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
The DAC5662 is available a 48-pin thin quad FlatPack (TQFP). Pin compatibility between family members provides 12-bit (DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5662 is pin compatible to the DAC2902 and AD9765 dual DACs. The device is characterized for operation over the industrial temperature range to 85 �C. AVAILABLE OPTIONS
MODE AVDD IOUTA1 IOUTA2 BIASJ_A EXTIO GSET BIASJ_B IOUTB2 IOUTB1 AGND SLEEP DA11 (MSB) DA1 DA0 (LSB)
TERMINAL NAME AGND AVDD BIASJ_A BIASJ_B CLKA/CLKIQ CLKB/RESETI DA[11:0] DB[11:0] DGND DVDD EXTIO 2 NO.
DESCRIPTION Analog ground Analog supply voltage Full-scale output current bias for DACA Full-scale output current bias for DACB Clock input for DACA, CLKIQ in interleaved mode. Clock input for DACB, RESETIQ in interleaved mode. Data port DA11 is MSB and DA0 is LSB. Data port DB11 is MSB and DB0 is LSB. Digital ground Digital supply voltage Internal reference output (bypass with �F to AGND) or external reference input.NC DGND DVDD WRTA/WRTIQ CLKA/CLKIQ CLKB/RESETIQ WRTB/SELECTIQ DGND DVDD DB11 (MSB) DB10
TERMINAL NAME GSET IOUTB1 IOUTB2 MODE NC SLEEP WRTA/WRTIQ WRTB/SELEC TIQ NO. I/O DESCRIPTION Gain-setting mode: - 1 resistor, - 2 resistors. Internal pullup. DACA current output. Full-scale with all bits of DA high. DACA complementary current output. Full-scale with all bits of DA low. DACB current output. Full-scale with all bits of DB high. DACB complementary current output. Full-scale with all bits of DB low. Mode Select: H � Dual Bus, L � Interleaved. Internal pullup. No connection Sleep function control input: H � DAC in power-down mode, L � DAC in operating mode. Internal pulldown. Input write signal for PORT A (WRTIQ in interleaving mode). Input write signal for PORT B (SELECTIQ in interleaving mode).