HomedatasheetDAC667JP

DAC667JP Datasheet

Ic-12-bit DAC
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Description

Features, Applications

FEATURES

q �3/4LSB MAX NONLINEARITY OVER TEMPERATURE q MONOTONICITY GUARANTEED OVER TEMPERATURE q MICROCOMPUTER INTERFACE: Double-Buffered Latch q VOLTAGE OUTPUT: �5V, +10V With to �15V Supplies q LOW POWER DISSIPATION: 345mW typ q PIN COMPATIBLE WITH AD667

DESCRIPTION

The is a complete monolithic integrated circuit microprocessor-compatible 12-bit digital-to-analog converter. It includes a precision voltage reference, microcomputer interface logic, double-buffered latch, and a 12-bit D/A converter with a voltage output amplifier. Fast current switches and a laser-trimmed thin-film resistor network provide a highly accurate and fast D/A converter. A double-buffered latch facilitates microcomputer interfacing or 16-bit data buses. The input buffer latch holds the 12-bit data until it is transferred to an internal 12-bit D/A converter latch, giving precise timing control over an analog output change. The DAC667 is specified to �1/2LSB maximum linearity error at +25�C. The DAC667 is guaranteed monotonic over the specification temperature range. The DAC667 is available 28-pin, 0.6" wide plastic DIP package.

�VEE 1 12-Bit D/A Converter 12-Bit Parallel Latch 5k 10V Span Summing Junction VOUT AGND Bipolar Offset 20V Span

International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

SPECIFICATIONS

�12V. �15V power supplies, unless otherwise noted. DAC667JP PARAMETER DIGITAL INPUTS Resolution Logic Levels (TTL Compatible, TMIN to TMAX)(1) VIH (Logic 1) VIL (Logic 0) IIH (VIH = 5.5V) IIL (VIL = 0.8V) ACCURACY Linearity Error TA = TMIN to TMAX Differential Linearity Error TA = TMIN to TMAX Gain Error(2) Unipolar Offset Error(2) Bipolar Zero(2) DRIFT Differential Linearity Gain (Full Scale), +25�C to TMIN or TMAX Unipolar Offset, +25�C to TMIN or TMAX Bipolar Zero, +25�C to TMIN or TMAX CONVERSION SPEED Settling Time �0.01% of FSR for FSR Change (2k 500pF Load, = 0) With 10k Feedback With 5k Feedback For LSB Change Slew Rate ANALOG OUTPUT Ranges(4) Output Current Output Impedance (DC) Short Circuit Current REFERENCE OUTPUT External Current POWER SUPPLY SENSITIVITY VCC to +16.5VDC VEE to �16.5VDC POWER SUPPLY REQUIREMENTS Rated Voltages Range(4) Supply Current to �16.5VDC TEMPERATURE RANGE Specification Operating Storage MIN TYP MAX Monotonicity Guaranteed UNITS Bits V �A LSB of FSR(3) LSB % of FSR ppm of FSR/�C

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

VCC to Power Ground.............................................................. to +18V VEE to Power Ground.............................................................. to �18V Digital Inputs (Pins 17�28) to Power Ground............. to +7V Ref In to Reference Ground.............................................................. �12V Bipolar Offset to Reference Ground................................................. �12V 10V Span Resistor to Reference Ground......................................... �12V 20V Span Resistor to Reference Ground......................................... �24V Ref Out, VOUT (Pins 6, 9).................... Indefinite Short to Power Ground, Momentary Short To VCC Power Dissipation........................................................................ 1000mW

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

LINEARITY ERROR max 25�C �1/2LSB GAIN TC, max (ppm/�C) �30 PACKAGE DRAWING NUMBER(1) 215

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

SYMBOL tDC tAC tCP tDH tSETT PARAMETER Data Valid to End of CS Address Valid to End of CS Pulse Width Data Hold Time Output Voltage Settling Time MIN TYP MAX UNITS ns �s

Write Cycle #1 Load first rank from Data Bus; 1. t tAC
A3 Write Cycle #2 Load second rank from first rank; = 1. tAC

Features

Parameters

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