HomedatasheetDAC725JP

DAC725JP Datasheet

ti DAC725, Dual 16-Bit Digital-to-analog Converter
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Description

Features, Applications

FEATURES

q COMPLETE DUAL VOUT DAC q DOUBLE-BUFFERED INPUT REGISTER q HIGH-SPEED DATA INPUT: Serial or Parallel q HIGH ACCURACY: �0.003% Linearity Error q 14-BIT MONOTONICITY OVER TEMPERATURE q PLASTIC PACKAGE q CLEAR INPUT TO SET ZERO OUTPUT

DESCRIPTION

The is a dual 16-bit DAC, complete with internal reference and output op amps. The DAC725 is designed to interface an 8-bit microprocessor bus, but can also be interfaced to wider buses. The hybrid construction minimizes the digital feedthrough typically associated with products that combine the digital bus interface circuitry with high-accuracy analog circuitry. The 16-bit data word is loaded into either of the DACs in two 8-bit bytes per 16-bit word. The versatility of the control lines allows the data word to be directed to either DAC, in any order. The voltage-out DACs are dedicated to a bipolar output voltage of �10V. The output is immediately set to 0V when the Clear command is given. This feature, combined with the bus interfacing and complete DAC circuitry, makes the DAC725 ideal for automatic test equipment, power control, servo systems, and robotics applications.

International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: Burr-Brown Corporation PDS-757D Printed in U.S.A. August, 1993

SPECIFICATIONS

= +25�C, VCC = �15V, and after a 10-minute warm-up unless otherwise noted. DAC725JP PARAMETER INPUT DIGITAL INPUT Resolution Bipolar Input Code Logic Levels(1): VIH VIL IIH (VI = +2.7V) IIL (VI = +0.4V) TRANSFER CHARACTERISTICS ACCURACY Linearity Error Differential Linearity Error(3) At Bipolar Zero: KP(3, 4) Gain Error(5) Bipolar Zero Error(5) Montonicity Over Specified Temp. Range Power Supply Sensitivity: +VCC, �VCC VDD DRIFT (Over Specified Temperature Range) Gain Drift Bipolar Zero Drift Differential Linearity Over Temperature(3) Linearity Error Over Temperature(3) SETTLING TIME (to FSR)(6) 20V Step (2k load) 1LSB Step at Worst-Case Code(7) Slew Rate OUTPUT Output Voltage Range(8) Output Current Output Impedance Short Circuit to Common Duration POWER SUPPLY REQUIREMENTS Voltage: +VCC �VCC VDD Current (No load, �15V supplies): +VCC �VCC VDD Power Dissipation (�15V supplies) TEMPERATURE RANGE Specification Storage *Specification same as model to the left. NOTES: (1) Digital inputs are TTL, LSTTL, 54/74HC and 54/74HTC compatible over the specification temperature range. (2) FSR means Full-Scale Range. For example, for �10V output, FSR �0.0015% of FSR is equal in 16-bit resolution. �0.003% of FSR is equal in 15-bit resolution. �0.006% of FSR is equal in 14-bit resolution. (4) Error at input code 0000H (BTC). (5) Adjustable to zero with external trim potentiometer. Adjusting the gain potentiometer rotates the transfer function around the bipolar zero point. (6) Maximum represents the 3 limit. Not tested for this parameter. (7) The bipolar worstcase code change is FFFFH to 0000H (BTC). (8) Minimum supply voltage for �10V output swing is approximately �13V. Output swing for �12V supplies is at least �5 0.15 Indefinite % of FSR % of FSR % of FSR Bits % of FSR/%VCC % of FSR/%VDD ppm/�C ppm of FSR/�C % of FSR % of FSR �s V/�s 16 Binary Twos Complement �A * Bits MIN TYP MAX MIN DAC725KP TYP MAX UNITS

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PIN 1 DESIGNATOR CLR DESCRIPTION Clear line. Sets the D/A register to 0000HEX, which gives bipolar zero on the D/A output. Logic supply (+5V). Latch enable for D/A latch (active low). Latch enable for "low byte" input (active low). Latch enable for "high byte" input (active low). Input for data bit 7 if enabling low byte (LB) latch, or data bit 15 if enabling the high byte (HB) latch. Input for data bit 6 if enabling LB latch, or data bit 14 if enabling HB latch. Data bit 5 (LB) or data bit 13 (HB). Data bit 4 (LB) or data bit 12 (HB). Data bit 3 (LB) or data bit 11 (HB). Data bit 2 (LB) or data bit 10 (HB). Data bit 1 (LB) or data bit 9 (HB). Data bit 0 (LB) or data bit 8 (HB). Digital common. Voltage output for DAC B. Analog common for DAC B. Summing junction of the internal op amp for DAC B. Gain adjust pin for DAC B. Write control line for DAC B. Chip select control line for DAC B. Positive supply voltage (+15V). Negative supply voltage (�15V). Chip select control line for DAC A. Write control line for DAC A. Voltage output for DAC A. Analog common for DAC A. Summing junction of the internal op amp for DAC A. Gain adjust pin for DAC A.

D0 (D8) DCOM VOUT (B) ACOM (B) SJ (B) GA (B) WR (B) CS (B) +VCC �VCC CS (A) WR (A) VOUT (A) ACOM (A) SJ (A) GA (A)

VDD to COMMON........................................................................ 0V, +15V +VCC to COMMON...................................................................... 0V, +18V �VCC to COMMON...................................................................... 0V, �18V Digital Data Inputs to COMMON...................................... �0.5V, VDD 0.5 DC Current any Input...................................................................... �10mA Reference Out to COMMON........................ Indefinite Short to COMMON VOUT............................................................ Indefinite Short to COMMON External Voltage Applied to RF......................................................... �18V External Voltage Applied to D/A Output............................................... �5V Power Dissipation........................................................................ 2000mW Storage Temperature...................................................... to +150�C Lead Temperature (soldering, 10s).................................................. 300�C NOTE: These devices are sensitive to electrostatic discharge. Appropriate I.C. handling procedures should be followed. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

MODEL DAC725JP DAC725KP PACKAGE 28-Pin Plastic DIP 28-Pin Plastic DIP PACKAGE DRAWING NUMBER(1) 215
MODEL DAC725JP DAC725KP LINEARITY ERROR max of FSR) �0.012 �0.006 TEMPERATURE RANGE to +70�C

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.


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