HomedatasheetDAC7545GLU

DAC7545GLU Datasheet

ti DAC7545, CMOS 12-Bit Multiplying D/A Converter, Microprocessor Compatible
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Description

Features, Applications

CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTER Microprocessor Compatible
FEATURES

FOUR-QUADRANT MULTIPLICATION LOW-GAIN TC: 2ppm/�C typ MONOTONICITY ENSURED OVER TEMPERATURE SINGLE TO 15V SUPPLY TTL/CMOS LOGIC COMPATIBLE LOW OUTPUT LEAKAGE: 10nA max LOW OUTPUT CAPACITANCE: 70pF max DIRECT REPLACEMENT FOR THE AD7545, PM-7545

DESCRIPTION

The is a low-cost, CMOS, 12-bit, four-quadrant multiplying, digital-to-analog converter (DAC) with input data latches. The input data is loaded into the DAC a 12-bit data word. The data flows through to the DAC when both the chip select (CS ) and the write (WR) pins are at a logic low. Laser-trimmed thin-film resistors and excellent CMOS voltage switches provide true 12-bit integral and differential linearity. The device operates on a single to +15V supply and is available an SO-20 package; devices are specified over the commercial temperature range. The DAC7545 is well suited for battery-powered or other lowpower applications because the power dissipation is less than 0.5mW when used with CMOS logic inputs and VDD = +5V.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

= +25�C, unless otherwise noted. VDD to DGND........................................................................... �0.3V, +17 Digital Input to DGND............................................................... �0.3V, VDD VRFB, VREF, to DGND........................................................................ �25V VPIN 1 to DGND........................................................................ �0.3V, VDD AGND to DGND........................................................................ �0.3V, VDD Power Dissipation: Any Package +75�C.................................... 450mW Derates above +75�C by................................ 6mW/�C Operating Temperature: Commercial K, L, and GL........................................... to +85�C Storage Temperature...................................................... to +150�C Lead Temperature (soldering, 10s)............................................... +300�C NOTE: (1) Stresses above those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

SPECIFIED RELATIVE GAIN ERROR (LSB) PACKAGE TEMPERATURE ACCURACY (LSB) VDD = +5V PACKAGE-LEAD DESIGNATOR(1) RANGE DW " PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY Rails,

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

Write Mode CS and WR low, DAC responds Data Bus (DB0-DB11) inputs. Mode Selection Hold Mode Either or WR high, data bus (DB0-DB11) is locked out; DAC holds last data present when or CS assumed high state.

NOTES: VDD = 20ns. VDD = 40ns. All inputs signal rise and fall times measured from 90% of VDD. Timing measurement reference level is (VIH + VIL)/2.

10-Bit Monotonic, TMIN to TMAX 10-Bit Monotonic, TMIN to TMAX 12-Bit Monotonic, TMIN to TMAX 12-Bit Monotonic, TMIN to TMAX DAC register loaded with FFFH. Gain error is adjustable using the circuits in Figures 2 and 3.

Gain Temperature Coefficient(3) (Gain/Temperature) DC Supply Rejection(3) (Gain/VDD) Output Leakage Current at Out 1 DYNAMIC PERFORMANCE Current Settling Time(3)

ppm/�C Typical Value is 2ppm/�C for VDD nA �s VDD = 0V; WR, To 1/2 LSB. Out 1 Load = 100 DAC output measured from falling edge of WR. = 0V.

Propagation Delay(3) (from digital input change 90% of final analog output) Glitch Energy AC Feedback at IOUT 1 REFERENCE INPUT Input Resistance (pin 19 to AGND) AC OUTPUTS Output Capacitance(3): COUT 1 COUT 2 DIGITAL INPUTS VIH (Input HIGH Voltage) VIL (Input LOW Voltage) IIN (Input Current)(7) Input Capacitance(3): DB0-DB11 WR, CS SWITCHING CHARACTERISTICS(8) Chip Select to Write Setup Time, tCS Chip Select to Write Hold Time, tCH Write Pulse Width, tWR Data Setup Time, tDS Data Hold Time, tDH POWER SUPPLY, IDD

All Digital Inputs VIL or VIH All Digital Inputs 0V or VDD All Digital Inputs 0V or VDD

NOTES: (1) Temperature ranges--J, K, L, and GL: +85�C. (2) This includes the effect of 5ppm max, gain TC. (3) Ensured but not tested. 0V to VDD or VDD 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25�C) is less than 1nA. (8) Sample tested +25�C to ensure compliance.


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