HomedatasheetDAC7802KP

DAC7802KP Datasheet

ti DAC7802, Dual Monolithic CMOS 12-Bit Multiplying Digital-to-analog Converter
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Description

Features, Applications

Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
FEATURES

q TWO DACs A 0.3" WIDE PACKAGE q SINGLE +5V SUPPLY q HIGH SPEED DIGITAL INTERFACE: Parallel--DAC7802 q MONOTONIC OVER TEMPERATURE q LOW CROSSTALK: �94dB min q FULLY SPECIFIED OVER TO +85OC

APPLICATIONS

PROCESS CONTROL OUTPUTS ATE PIN ELECTRONICS LEVEL SETTING PROGRAMMABLE FILTERS PROGRAMMABLE GAIN CIRCUITS AUTO-CALIBRATION CIRCUITS

DESCRIPTION

The DAC7800, DAC7801 and DAC7802 are members of a new family of monolithic dual 12-bit CMOS multiplying Digital-to-Analog Converters (DACs). The digital interface speed and the AC multiplying performance are achieved by using an advanced CMOS process optimized for data conversion circuits. High stability on-chip resistors provide true 12-bit integral and differential linearity over the wide industrial temperature range +85�C. DAC7800 features a serial interface capable of clocking-in data at a rate of at least 10MHz. Serial data is clocked (edge triggered) MSB first into a 24-bit shift register and then latched into each DAC separately or simultaneously as required by the application. An asynchronous CLEAR control is provided for power-on reset or system calibration functions. It is packaged 16-pin 0.3" wide plastic DIP. DAC7801 has + 4) double-buffered interface. Data is first loaded (level transferred) into the input registers in two steps for each DAC. Then both DACs are updated simultaneously. DAC7801 features an asynchronous CLEAR control. DAC7801 is packaged 24-pin 0.3" wide plastic DIP. DAC7802 has a single-buffered 12-bit data word interface. Parallel data is loaded (edge triggered) into the single DAC register for each DAC. DAC7802 is packaged 24-pin 0.3" wide plastic DIP.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

= +25�C, unless otherwise noted. VDD to AGND.................................................................................. 0V, +7V VDD to DGND.................................................................................. 0V, +7V AGND to DGND.......................................................................... �0.3, VDD Digital Input to DGND........................................................ �0.3, VDD + 0.3 VREF A, VREF B to AGND..................................................................... �16V VREF A, VREF B to DGND..................................................................... �16V IOUT A, IOUT B to AGND................................................................. �0.3, VDD Storage Temperature Range........................................... to +125�C Operating Temperature Range......................................... to +85�C Lead Temperature (soldering, 10s)................................................. +300�C Junction Temperature...................................................................... +175�C

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

RELATIVE ACCURACY �1LSB �1/2 LSB �1LSB �1/2 LSB �1LSB �1/2 LSB GAIN ERROR �3LSB �1LSB PACKAGE NT DW NTG DW SPECIFIED TEMPERATURE RANGE to +85�C PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY Rails, 25 Rails, 25 and Reel, 1000 and Reel, 1000 Rails, 15 Rails, 15 and Reel, 1000 and Reel, 1000 Rails, 15 Rails, 15 and Reel, 1000 and Reel, 1000

DAC7800KU DAC7800KU/1K Tape DAC7800LU DAC7800LU/1K Tape DAC7801KU DAC7801KU/1K Tape DAC7801LU DAC7801LU/1K Tape DAC7802KU DAC7802KU/1K Tape DAC7802LU DAC7802LU/1K Tape

NOTE: (1 ) For the most current specifications and package information, refer to our web site at www.ti.com.

At VDD = +5VDC, VREF A = VREF to +85�C, unless otherwise noted. 7801, 7802K PARAMETER ACCURACY Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Temperature Coefficient(1) Output Leakage Current REFERENCE INPUT Input Resistance Input Resistance Match DIGITAL INPUTS VIH (Input HIGH Voltage) VIL (Input LOW Voltage) IIN (Input Current) CIN (Input Capacitance) POWER SUPPLY VDD IDD Power-Supply Rejection 4.5 0.2 VDD from to 5.5V CONDITIONS MIN TYP MAX 7801, 7802L MIN �1 2 TYP MAX UNITS Bits LSB ppm/�C V mA

OUTPUT OP AMP OPA602. At VDD = +5VDC, VREF A = VREF = +25�C, unless otherwise noted. These specifications are fully characterized but not subject to test. 7801, 7802K PARAMETER OUTPUT CURRENT SETTLING TIME DIGITAL-TO-ANALOG GLITCH IMPULSE AC FEEDTHROUGH OUTPUT CAPACITANCE CHANNEL-TO-CHANNEL ISOLATION VREF A to IOUT B CONDITIONS 0.01% of Full-Scale = 13pF VREF A = VREF = 13pF fVREF = 10kHz DAC Loaded with All 0s DAC Loaded with All 1s fVREF = 10kHz VREF = 0V, Both DACs Loaded with 1s fVREF = 10kHz VREF = 0V, Both DACs Loaded with 1s Full-Scale Transition 13pF �90 MIN TYP MAX 7801, 7802L MIN TYP MAX UNITS �s nV-s pF dB

VDD 12 DAC7800 Control Logic and Shift Register 12 DAC B Register 12 DAC B Bit 0 Bit 11 Bit 12 Bit 23 DAC A 12 DAC A Register Data In 11 CLR 9 DGND UPD B I OUT B AGND B RFB B V REF B VREF A I OUT A AGND A UPD A

AGND A I OUT FB A VREF A CLK UPD A Data CS DAC7800 AGND B IOUT FB B VREF B VDD CLR UPD B DGND

CLK UPD CS X CLR 0 X FUNCTION All register contents set to 0's (asynchronous). No data transfer. Input data is clocked into input register (location Bit 23) and previous data shifts. Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A. Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B. Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.


Features

Parameters

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