FEATURES 12-Bit Accuracy an 8-Pin Mini-DIP Fast Serial Data Input Double Data Buffers Low 1/2 LSB Max INL and DNL Max Gain Error: 1 LSB Low 5 ppm/ C Max Tempco ESD Resistant Low Cost Available in Die Form APPLICATIONS Autocalibration Systems Process Control and Industrial Automation Programmable Amplifiers and Attenuators Digitally-Controlled FiltersPIN CONNECTIONS GENERAL DESCRIPTION 8-Pin Epoxy DIP (P-Suffix) 8-Pin Cerdip (Z-Suffix)
The is a high accuracy 12-bit CMOS multiplying DAC in a space-saving 8-pin mini-DIP package. Featuring serial data input, double buffering, and excellent analog performance, the DAC8043 is ideal for applications where PC board space at a premium. Also, improved linearity and gain error performance permit reduced parts count through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. The circuit consists a 12-bit serial-in, parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the D/A converter. The DAC8043's fast interface timing may reduce timing design considerations while minimizing microprocessor wait states. For applications requiring an asynchronous CLEAR function or more versatile microprocessor interface logic, refer to the PM-7543. Operating from a single +5 V power supply, the DAC8043 is the ideal low power, small size, high performance solution to many application problems. It is available in plastic and cerdip packages that are compatible with auto-insertion equipment.TOP VIEW IOUT 5 (Not to Scale) 12 SRI GND 6 GND 7 N.C. LD 10 N.C. 9 N.C.
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STATIC ACCURACY Resolution Nonlinearity (Note 1) Differential Nonlinearity (Note 2) Gain Error (Note 3)
DD REF +10 V; IOUT = GND TA = Full Temperature Range specified under Absolute Maximum Ratings unless otherwise noted).
Gain Tempco ( Gain/ Temp) (Note 5) Power Supply Rejection Ratio ( Gain/ VDD) Output Leakage Current (Note 4)TCGFS VDD TA = Full Temperature Range TA = Full Temperature Range DAC8043A DAC8043E/F/G
Input Resistance (Note 8) AC PERFORMANCE Output Current Settling Time (Notes 5, 6) Digital to Analog Glitch Energy (Note 5, 10) Feedthrough Error (VREF to IOUT) (Note 5, 11) Total Harmonic Distortion (Note 5) Output Noise Voltage Density (Note 5, 13) DIGITAL INPUTS Digital Input HIGH Digital Input LOW Input Leakage Current (Note 9) Input Capacitance (Note 5, 11) ANALOG OUTPUTS Output Capacitance (Note 5)
= +25�C VREF 0 V IOUT Load = 100 CEXT 13 pF DAC Register Loaded Alternately with All 0s and All 1s VREF 20 V p-p = 10 kHz Digital Input = +25�C VREF 6 V rms @ 1 kHz DAC Register Loaded with All to 100 kHz between RFB and IOUT
Parameter Symbol Conditions Min Typ Max Units TIMING CHARACTERISTICS (NOTES 5, 14) Data Setup Time tDS Data Hold Time tDH Clock Pulse Width High tCH Clock Pulse Width Low tCL Load Pulse Width tLD LSB Clock Into Input Register to Load DAC Register Time tASB POWER SUPPLY Supply Voltage Supply Current VDD IDD
TA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range
NOTES � 1/2 LSB 0.012% of full scale. 12 All grades are monotonic to 12-bits over temperature. 13 Using internal feedback resistor. 14 Applies to I OUT; All digital inputs V. 15 Guaranteed by design and not tested. 16 IOUT Load 100 , CEXT = 13 pF, digital input DD or VDD 0 V. Extrapolated to 1/2 LSB; S = propagation delay (t PD) + 9 where = measured time constant of the final RC decay. 17 VREF +10 V, all digital inputs V. 18 Absolute temperature coefficient is less than +300 ppm/ �C. 19 Digital inputs are CMOS gates; IN is typically at +25 �C. 10 VREF 0 V, all digital inputs DD or VDD V. 11 All digit inputs V. 12 Calculated from worst case R REF: IZSE (in LSBs) = (RREF � ILKG 4096)/VREF. 13 Calculations from = 4K TRB where: K = Boltzmann constant, J/ �K, R = resistance, T = resistor temperature, �K, B = bandwidth, Hz. 14 Tested at VIN V or VDD. Specifications subject to change without notice.
VDD GND.+17 V VREF to GND. 25 V VRFB to GND. 25 V Digital Input Voltage Range. V to VDD Output Voltage (Pin V to VDD Operating Temperature Range AZ Versions. to +125�C EZ/FZ/FP Versions. +85�C GP Version. to +70�C Junction Temperature. +150�C Storage Temperature. to +150�C Lead Temperature (Soldering, 60 sec). +300�C Package Type 8-Pin Hermetic DIP (Z) 8-Pin Plastic DIP (P) JA* 12 37 Units �C/W
1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF (Pin 1) and RFB (Pin 2). 2. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper antistatic handling procedures. 4. Absolute Maximum Ratings apply to both packaged devices and DICE. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Model DAC8043GP DAC8043HP Relative Accuracy � 1/2 LSB � 1/2 LSB � 1/2 LSB � 1 LSB � 1 LSB � 1 LSB � 1/2 LSB � 1 LSB Temperature Range to +70�C Package Option 8-Pin Cerdip 8-Pin Cerdip 8-Pin Cerdip 16-Lead (Wide) SOL 8-Pin Cerdip 8-Pin Epoxy DIP 8-Pin Epoxy DIP 8-Pin Epoxy DIP
*JA is specified for worst case mounting conditions, i. e., JA is specified for device in socket for cerdip and P-DIP packages.
NOTES 1 All commercial and industrial temperature range parts are available with burn-in. 2 For devices processed in total compliance MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet.
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