HomedatasheetDAC813KP

DAC813KP Datasheet

ti DAC813, Microprocessor-compatible 12-Bit D/A Converter
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Description

Features, Applications

FEATURES

q �1/2LSB NONLINEARITY OVER TEMPERATURE q GUARANTEED MONOTONIC OVER TEMPERATURE q LOW POWER: 270mW typ q DIGITAL INTERFACE DOUBLE BUFFERED: 12 AND + 4 BITS q SPECIFIED AT �12V AND �15V POWER SUPPLIES q RESET FUNCTION TO BIPOLAR ZERO q 0.3" WIDE DIP AND SO PACKAGES converter with voltage output operational amplifier. Fast current switches and laser-trimmed thin-film resistors provide a highly accurate, fast D/A converter. Digital interfacing is facilitated by a double buffered latch. The input latch consists of one 8-bit byte and one 4-bit nibble to allow interfacing to 8-bit (right justified format) or 16-bit data buses. Input gating logic is designed so that the last nibble or byte to be loaded can be loaded simultaneously with the transfer of data to the D/A latch saving computer instructions. A reset control allows the DAC813 D/A latch to asynchronously reset the D/A output to bipolar zero, a feature useful for power-up reset, recalibration, or for system re-initialization upon system failure. The DAC813 is specified to �1/2LSB maximum linearity error (J, A grades) and �1/4LSB (K grade). It is packaged 28-pin 0.3" wide plastic DIP and 28-lead plastic SOIC

DESCRIPTION

The is a complete monolithic 12-bit digitalto-analog converter with a flexible digital interface. It includes a precision +10V reference, interface control logic, double-buffered latch and a 12-bit D/A

International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

SPECIFICATIONS

= +25�C, �VCC or �15V and load on VOUT 500pF to common, unless otherwise noted. DAC813JP, JU, AU PARAMETER DIGITAL INPUTS Resolution Codes(1) Digital Inputs Over Temperature Range(2) VIH(3) VIL DATA Bits, WR, Reset, LDAC, LMSB, LLSB IIH IIL ACCURACY Linearity Error Differential Linearity Error Gain Error(4) Unipolar Offset Error(5) Bipolar Zero Error(6) Monotonicity Power Supply Sensitivity: +VCC �VCC DRIFT Gain Unipolar Offset Bipolar Zero Linearity Error Over Temperature Range Monotonicity Over Temperature Range SETTLING TIME(8) (To Within �0.01% of FSR of Final Value; 5k 500pF load) For Full Scale Range Change For 1LSB Change at Major Carry(9) Slew Rate ANALOG OUTPUT Voltage Range: Unipolar Bipolar Output Current Output Impedance Short Circuit to Common Duration REFERENCE VOLTAGE Voltage Source Current Available for External Loads Impedance Temperature Coefficient Short Circuit to Common Duration POWER SUPPLY REQUIREMENTS Voltage: +VCC �VCC Current: +VCC + VL �VCC Potential at DCOM with Respect to ACOM(10) Power Dissipation TEMPERATURE RANGE Specification: K A Operating: K A Storage: A T Same as specification for DAC813AU, JP, JU. NOTES: (1) USB = Unipolar Straight Binary; BOB = Bipolar Offset Binary. (2) TTL and 5V CMOS compatible. (3) Open DATA input lines will be pulled above +5.5V. See discussion under LOGIC INPUT COMPATIBILITY in the OPERATION section. (4) Specified with 500 Pin to 7. Adjustable to zero with external trim potentiometer. (5) Error at input code 000HEX for unipolar mode, FSR 10V. (6) Error at input code 800HEX for bipolar range. Specified with 100 Pin to 4 and with 500 pin to 7. See page 9 for zero adjustment procedure. (7) FSR means Full Scale Range and is 20V for the �10V range. (8) Maximum represents the 3 limit. Not 100% tested for this parameter. (9) At the major carry, to 800HEX and 7FFHEX. (10) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications. �VCC > �11.4V �VCC At DC CONDITIONS MIN TYP MAX 12 USB, BOB +2 0 VIN = +2.7V VIN = +0.4V Guaranteed VDC �A MIN DAC813KP, KU TYP MAX T UNITS Bits


PIN NAME +VL 20V Range BPO DESCRIPTION Positive supply pin for logic circuits. Connect to +VCC. Connect Pin 2 or Pin 3 to Pin 9 (VOUT) for a 20V FSR. Connect both to Pin 9 for a 10V FSR. Bipolar offset. Connect to Pin 6 (VREF OUT) through 100 resistor or 200 potentiometer for bipolar operation. Analog common, �VCC supply return. +10V reference output referred to ACOM. Connected to VREF OUT through a 1k gain adjustment potentiometer a 500 resistor. Analog supply input, nominally to +15V referred to ACOM. D/A converter voltage output. Analog supply input, nominally or �15V referred to ACOM. Master enable for LDAC, LLSB, and LMSB. Must be low for data transfer to any latch. Load DAC. Must be low with WR for data transfer to the D/A latch and simultaneous update of the D/A converter. When low, resets the D/A latch such that a Bipolar Zero output is produced. This control overrides all other data input operations. Enable for 4-bit input latch of D8-D11 data inputs. NOTE: This logic path is slower than the WR path. Enable for 8-bit input latch of D0-D7 data inputs. NOTE: This logic path is slower than the WR path. Digital common. Data Bit 1, LSB. Data Bit 2. Data Bit 3. Data Bit 4. Data Bit 5. Data Bit 6. Data Bit 7. Data Bit 8. Data Bit 9. Data Bit 10. Data Bit 11. Data Bit 12, MSB, positive true.

+VCC to ACOM.......................................................................... to +18V �VCC to ACOM.......................................................................... to �18V +VCC to �VCC............................................................................ to +36V DCOM with respect to ACOM............................................................. �4V Digital Inputs (Pins 17�28) to DCOM.................... �0.5V to +VCC External Voltage Applied to BPO Span Resistor.............................. �VCC VREF OUT........................................................... Indefinite Short to ACOM VOUT................................................................. Indefinite Short to ACOM Power Dissipation.......................................................................... 750mW Lead Temperature (soldering, 10s)............................................... +300�C Max Junction Temperature............................................................ +165�C Thermal Resistance, J-A:Plastic DIP and SOIC........................ 130�C/W Ceramic DIP......................................... 85�C/W NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.

ACOM VREF OUT VREF IN +VCC VOUT �VCC WR LDAC

Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications.

PACKAGE DRAWING NUMBER(1) TEMPERATURE RANGE to +85�C LINEARITY ERROR, MAX AT +25�C (LSB) GAIN DRIFT (ppm/�C)

PACKAGE 28-Pin Plastic DIP 28-Lead Plastic SOIC 28-Pin Plastic DIP 28-Lead Plastic SOIC 28-Lead Plastic SOIC

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.


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