FEATURES Fast, Flexible, Microprocessor Interfacing in Serially Controlled Systems Buffered Digital Output Pin for Daisy-Chaining Multiple DACs Minimizes Address-Decoding in Multiple DAC Systems--Three-Wire Interface for Any Number of DACs One Data Line One CLK Line One Load Line Improved Resistance to ESD +85 C for the Extended Industrial Temperature Range APPLICATIONS Multiple-Channel Data Acquisition Systems Process Control and Industrial Automation Test Equipment Remote Microprocessor-Controlled Systems GENERAL INFORMATION
VREF 12-BIT D/A CONVERTER IOUT1 IOUT2 CLR STB3 STB2 SRI IN CLK INPUT 12-BIT SHIFT REGISTER OUT SRO AGND
The a 12-bit serial-input daisy-chain CMOS D/A converter that features serial data input and buffered serial data output. It was designed for multiple serial DAC systems, where serially daisy-chaining one DAC after another is greatly simplified. The DAC8143 also minimizes address decoding lines enabling simpler logic interfacing. It allows three-wire interface for any number of DACs: one data line, one CLK line and one load line. Serial data in the input register (MSB first) is sequentially clocked out to the SRO pin as the new data word (MSB first) is simultaneously clocked in from the SRI pin. The strobe inputs are used to clock in/out data on the rising or falling (user selected) strobe edges STB3, STB4). When the shift register's data has been updated, the new data word is transferred to the DAC register with use of LD1 and LD2 inputs. Separate LOAD control inputs allow simultaneous output updating of multiple DACs. An asynchronous CLEAR input resets the DAC register without altering data in the input register. Improved linearity and gain error performance permits reduced circuit parts count through the elimination of trimming components. Fast interface timing reduces timing design considerations while minimizing microprocessor wait states. The DAC8143 is available in plastic packages that are compatible with autoinsertion equipment. Plastic packaged devices come in the extended industrial temperature range to +85�C. REV. C
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Parameter STATIC ACCURACY Resolution Nonlinearity Differential Nonlinearity1 Gain Error2 Gain Tempco (Gain/Temp)3 Power Supply Rejection Ratio (Gain/VDD) Output Leakage Current4 Zero Scale Error5, 6 Input Resistance7 AC PERFORMANCE Output Current Settling 8 AC Feedthrough Error (VREF IOUT1)3, 9 Digital-to-Analog Glitch Energy3, 10 Total Harmonic Distortion3 Output Noise Voltage Density3, 11 DIGITAL INPUTS/OUTPUT Digital Input HIGH Digital Input LOW Input Leakage Current12 Input Capacitance Digital Output High Digital Output Low ANALOG OUTPUTS Output Capacitance3 Output Capacitance3 TIMING CHARACTERISTICS3 Serial Input to Strobe Setup Times (tSTB = 80 ns) Symbol N INL DNL GFSE TCGFS PSRR ILKG IZSE RIN FT Q THD en VIH VIL IIN CIN VOH VOL tDH1 tDH2 Serial Input to Strobe Hold Times (tSTB = 80 ns) VREF 20 V p-p = 10 kHz, = +25�C VREF 0 V, IOUT Load 100 , CEXT 13 pF VREF 6 V rms @ 1 kHz DAC Register Loaded with All to 100 kHz Between RFB and IOUT 2.4 VIN +5 V VIN 0 V IOH �200 �A IOL 1.6 mA Digital Inputs = All 1s Digital Inputs = All 0s Digital Inputs = All 0s Digital Inputs = All 1s STB1 Used as the Strobe STB2 Used as the Strobe STB3 Used as the Strobe TA = Full Temperature Range STB4 Used as the Strobe STB1 Used as the Strobe TA = Full Temperature Range STB2 Used as the Strobe TA = Full Temperature Range STB3 Used as the Strobe STB4 Used as the Strobe VDD TA = Full Temperature Range TA = Full Temperature Range VREF Pin
VDD +5 V; VREF VOUT2 = VAGND = VDGND TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)
VDD +5 V; VREF V0UT2 = VAGND = VDGND TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)
Symbol tPD tSRI tLD1, tLD2 Conditions TA = Full Temperature Range All Digital Inputs = VIH or VIL All Digital Inputs V or VDD Digital Inputs V or VDD 0.1 mA Digital Inputs = VIH or VIL mA Min DAC8143 Typ Max 220 300 Units mA mW
SRI Data Pulsewidth STB1 Pulsewidth ns)14 STB2 Pulsewidth ns)14 STB3 Pulsewidth ns)14 STB4 Pulsewidth 80 ns)14 Load Pulsewidth LSB Strobe into Input Register to Load DAC Register Time CLR Pulsewidth POWER SUPPLY Supply Voltage Supply Current Power Dissipation
NOTES 11 All grades are monotonic to 12 bits over temperature. 12 Using internal feedback resistor. 13 Guaranteed by design and not tested. 14 Applies to IOUT1; all digital inputs = V IL, VREF +10 V; specification also applies for I OUT2 when all digital inputs = V IH. 15 VREF +10 V, all digital inputs V. 16 Calculated from worst case R REF: IZSE (in LSBs) = (RREF � ILKG � 4096) /VREF. 17 Absolute temperature coefficient is less than +300 ppm/ �C. 18 IOUT, Load = 100. CEXT = 13 pF, digital input DD or VDD 0 V. Extrapolated to 1/2 LSB: S = propagation delay (t PD) +9 , where equals measured time constant of the final RC decay. 19 All digital inputs V. 10 VREF 0 V, all digital inputs DD or VDD V. 11 Calculations from = 4K TRB where: K = Boltzmann constant, J/KR = resistance T = resistor temperature, B = bandwidth, Hz 12 Digital inputs are CMOS gates; I IN typically at +25 �C. 13 Measured from active strobe edge (STB) to new data output at SRO; = 50 pF. 14 Minimum low time pulsewidth for STB 1, STB2, and STB4, and minimum high time pulsewidth for STB 3. Specifications subject to change without notice.
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