DAC8248H Datasheet

Dual 12-Bit (8-Bit Byte) Double-buffered CMOS D/A Converter


Features, Applications

PIN CONNECTIONS 24-Pin 0.3" Cerdip (W Suffix), 24-Pin Epoxy DIP (P Suffix), 24-Pin SOL (S Suffix)

FEATURES Two Matched 12-Bit DACs on One Chip 12-Bit Resolution with an 8-Bit Data Bus Direct Interface with 8-Bit Microprocessors Double-Buffered Digital Inputs RESET to Zero Pin 12-Bit Endpoint Linearity ( 1/2 LSB) Over Temperature 15 V Single Supply Operation Latch-Up Resistant Improved ESD Resistance Packaged in a Narrow 0.3" 24-Pin DIP and 0.3" 24-Pin SOL Package Available in Die Form APPLICATIONS Multichannel Microprocessor-Controlled Systems Robotics/Process Control/Automation Automatic Test Equipment Programmable Attenuator, Power Supplies, Window Comparators Instrumentation Equipment Battery Operated Equipment GENERAL DESCRIPTION

The DAC8248's double-buffered digital inputs allow both DAC's analog output to be updated simultaneously. This is particularly useful in multiple DAC systems where a common LDAC signal updates all DACs at the same time. A single RESET pin resets both outputs to zero. The DAC8248's monolithic construction offers excellent DACto-DAC matching and tracking over the full operating temperature range. The DAC consists of two thin-film R-2R resistor ladder networks, two 12-bit, two 8-bit, and two 4-bit data registers, and control logic circuitry. Separate reference input and feedback resistors are provided for each DAC. The DAC8248

The is a dual 12-bit, double-buffered, CMOS digitalto-analog converter. It has an 8-bit wide input data port that interfaces directly with 8-bit microprocessors. It loads a 12-bit word in two bytes using a single control; it can accept either a least significant byte or most significant byte first. For designs with or 16-bit wide data path, choose the or DAC8221.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Parameter STATIC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Full-Scale Gain Error1 Symbol N INL DNL GFSE

+15 V; VREF A = VREF +10 V; VOUTA = VOUT 0 V; AGND = DGND TA = Full Temp Range specified in Absolute Maximum Ratings; unless otherwise noted. Specifications apply for DAC A and DAC B.)

DAC8248A/E/G DAC8248F/H All Grades are Guaranteed Monotonic DAC8248G DAC8248F/H (Notes 2, 3) All Digital Inputs TA = Full Temperature Range (Note VDD +5 V VDD +15 V VDD +5 V VDD TA = Full Temperature Range DB0�DB11 WR, LDAC, DAC A/DAC B, LSB/MSB, RESET Digital Inputs = VINL or VINH Digital Inputs V or VDD � 5%

Gain Temperature Coefficient (Gain/Temperature) Output Leakage Current IOUT A (Pin 2), IOUT B (Pin 24) Input Resistance (VREF A, REF B) Input Resistance Match DIGITAL INPUTS Digital Input High Digital Input Low Input Current (VIN V or VDD and VINL or VINH) Input Capacitance (Note 2) POWER SUPPLY Supply Current DC Power Supply Rejection Ratio (Gain/VDD)

AC PERFORMANCE CHARACTERISTICS Propagation Delay5, 6 tPD Output Current Setting 7 tS Output Capacitance CO

= +25�C Digital Inputs = All 0s COUT A, COUT B Digital Inputs = All 1s COUT A, COUT B VREF A to IOUT A; VREF 20 V p-p = 100 kHz; = +25�C VREF B to IOUT B; VREF 20 V p-p = 100 kHz; = +25�C

Parameter Switching Characteristics (Notes 2, 8) LSB/MSB Select to Write Set-Up Time LSB/MSB Select to Write Hold Time DAC Select to Write Set-Up Time DAC Select to Write Hold Time LDAC to Write Set-Up Time LDAC to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width LDAC Pulse Width Reset Pulse Width tCBS tCBH tAS tAH tLS tLH tDS tDH tWR tLWD tRWD Symbol Conditions VDD to +85C (Note DAC8248 VDD to +125C All Temps (Note ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Units

NOTES 11 Measured using internal FB A and RFB B. Both DAC digital inputs Guaranteed and not tested. 13 Gain TC is measured from �C to TMIN or from +25�C to TMAX. 14 Absolute Temperature Coefficient is approximately +50 ppm/ �C. 15 From 50% of digital input 90% of final analog output current. V REF A = VREF +10 V; OUT A, OUT B load 100 , CEXT = 13 pF. 16 WR, LDAC DD or VDD V. 17 Settling time is measured from 50% of the digital input change to where the output settles within 1/2 LSB of full scale. 18 See Timing Diagram. 19 These limits apply for the commercial and industrial grade products. 10 These limits also apply as typical values for +12 V with +5 V CMOS logic levels and = +25�C. Specifications subject to change without notice.



Manufacturer information

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