FEATURES Four DACs a 28 Pin, 0.6 Inch Wide DIP or 28-Pin JEDEC Plastic Chip Carrier 1/4 LSB Endpoint Linearity Guaranteed Monotonic DACs Matched to Within 1% Microprocessor Compatible Read/Write Capability (with Memory) TTL/CMOS Compatible Four-Quadrant Multiplication Single-Supply Operation (+5 V) Low Power Consumption Latch-Up Resistant Available In Die Form APPLICATIONS Voltage Set Points in Automatic Test Equipment Systems Requiring Data Access for Self-Diagnostics Industrial Automation Multichannel Microprocessor-Controlled Systems Digitally Controlled Op Amp Offset Adjustment Process Control Digital AttenuatorsQuad 8-Bit Multiplying CMOS D/A Converter with Memory DAC8408
A common 8-bit TTL/CMOS compatible input port is used to load data into any of the four DAC data-latches. Control lines DS1, DS2, and A/B determine which DAC will accept data. Data loading is similar to that of a RAMs write cycle. Data can be read back onto the same data bus with control line R/W. The DAC8408 is bus compatible with most 8-bit microprocessors, including the 8080, 8085, and Z80. The DAC8408 operates on a single +5 volt supply and dissipates less than 20 mW. The DAC8408 is manufactured using PMI's highly stable, thin-film resistors on an advanced oxide-isolated, silicon-gate, CMOS process. PMI's improved latch-up resistant design eliminates the need for external protective Schottky diodes.
28-Pin Plastic DIP 28-Pin Cerdip 28-Pin Cerdip 28-Pin Cerdip 28-Pin Cerdip 28-Contact PLCC 28-Pin SOL 28-Pin Plastic DIP
The is a monolithic quad 8-bit multiplying digital-toanalog CMOS converter. Each DAC has its own reference input, feedback resistor, and onboard data latches that feature read/write capability. The readback function serves as memory for those systems requiring self-diagnostics.
NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. For outline information see Package Information section. 2 For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. 3 For availability and burn-in information on SO and PLCC packages, contact your local sales office.
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Parameter STATIC ACCURACY Resolution Nonlinearity1, 2 Differential Nonlinearity Gain Error Gain Tempco3, 6 Power Supply Rejection (VDD � 10%) IOUT C, D Leakage Current13 REFERENCE INPUT Input Voltage Range Input Resistance Match4 Input Resistance DIGITAL INPUTS Digital Input Low Digital Input High Input Current5 Input Capacitance6 DATA BUS OUTPUTS Digital Output Low Digital Output High Output Leakage Current DAC OUTPUTS6 Propagation Delay7 Settling Time11,12 Output Capacitance AC Feedthrough SWITCHING CHARACTERISTICS Write to Data Strobe Time Data Valid to Strobe Set-Up Time Data Valid to Strobe Hold Time DAC Select to Strobe Set-Up Time DAC Select to Strobe Hold Time Write Select to Strobe Set-Up Time Write Select to Strobe Hold Time Read to Data Strobe Width Data Strobe to Output Valid Time Output Data to Deselect Time Read Select to Strobe Set-Up Time Read Select to Strobe Hold Time
VDD +5 V; VREF 10 V; VOUTA, to +125C apply for to +85C apply for to +70C apply for DAC8408GP, unless otherwise noted. Specifications apply for DAC C, & D.)
Symbol N INL DNL GFSE TCGFS PSR ILKG TA = Full Temperature Range Conditions Min DAC8408A/E/G DAC8408B/F/H (Using Internal RFB) DAC8408 Typ Max Units Bits LSB ppm/�C %FSR/% dB ns REV. AtPD tS COUT or tDS2 tDSU tDH tAS tAH tWSU tWH tRDS tCO tOTD tRSU tRH
DAC Latches All "0s" DAC Latches All "1s" (20 Vp-p = 100 kHz) TA = Full Temperature Range TA = Full Temperature RangeTA = Full Temperature Range TA = Full Temperature Range TA = Full Temperature Range
@ VDD +5 V; VREF 10 V; VOUTA, to +125C apply for to +85C apply for to +70C apply for DAC8408GP, unless otherwise noted. Specifications apply for DAC & D. Continued
Parameter POWER SUPPLY Voltage Range Supply Current8 Supply Current9 Symbol VDD IDD Conditions Min TA = Full Temperature Range
NOTES 1 This is an end-point linearity specification. 2 Guaranteed to be monotonic over the full operating temperature range. 3 ppm/�C of FSR (FSR = Full Scale Range = VREF-1 LSB.) 4 Input Resistance Temperature Coefficient = +300ppm/ �C. 5 Logic Inputs are MOS gates. Typical input current +25�C Is less than 10 nA. 6 Guaranteed by design.
From Digital Input 90% of final analog output current. All Digital Inputs or V DD. All Digital Inputs IH or VIL. 10 See Timing Diagram. 11 Digital Inputs DD or VDD V. 12 Extrapolated: S (1/2 LSB) = tPD + 6.2 where = the measured first time constant of the final RC decay. 13 All Digital Inputs V; V REF +10 V. Specifications subject to change without notice.Package Type 28-Pin Hermetic DIP (T) 28-Pin Plastic DIP (P) 28-Pin SOL (S) 28-Contact PLCC (PC)
VDD to IOUT 2A, IOUT 2B, IOUT 2C, IOUT +7 V VDD to DGND. +7 V IOUT 1A, IOUT 1B, IOUT 1C, IOUT 1D to DGND. V to VDD +0.3 V RFBA, RFBB, RFBC, RFBD to IOUT. 25 V IOUT 2A, IOUT 2B, IOUT 2C, IOUT 2D to DGND. V to VDD V DB0 through DB7 to DGND. V to VDD 0.3 V Control Logic Input Voltage to DGND. V + VDD 0.3 V VREFA, VREFB, VREFC, VREFD to IOUT 2A, IOUT 2B, IOUT 2C, IOUT 25 V Operating Temperature Range Commercial Grade (GP). to +70�C Industrial Grade (ET, FT, FP, FPC, FS). to +85�C Military Grade (AT, BT). to +125�C Junction Temperature. +150�C Storage Temperature. to +150�C Lead Temperature (Soldering, 10 sec). +300�C
*JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and P-DIP packages; JA is specified for device soldered to printed circuit board for SOL and PLCC packages.
1. Do not apply voltages higher than VDD V or less than �0.3 V potential on any terminal except VREF and RFB. 2. The digital control inputs are diode-protected; however, permanent damage may occur on unconnected inputs from high energy electrostatic fields. Keep in conductive foam at all times until ready to use. 3. Use proper antistatic handling procedures. 4. Absolute Maximum Ratings apply to both packaged devices and DICE. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.