16-BIT, QUAD CHANNEL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
Relative Accuracy: 12 LSB (Max) Glitch Energy: 0.15 nV-s Power Supply: +5.5 V MicroPower Operation: V 16-Bit Monotonic Over Temperature Settling Time: to �0.003% FSR Power-On Reset to Zero-Scale and Mid-Scale Binary and 2's Complement Capability Ultra-Low AC Crosstalk: �100 dB Typ On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Double Buffered Input Architecture Simultaneous or Sequential Output Update and Power-Down Asynchronous Clear to Zero-Scale and Mid-Scale Schmitt-Triggered Inputs SPI Compatible Serial Interface: to 50 MHz. 5.5 V Logic Compatibility Available a TSSOP-16 PackageDESCRIPTION
The a 16-bit, quad channel voltage output digital-to-analog converter (DAC) offering low-power operation and a flexible serial host interface. It offers monotonicity, good linearity, and exceptionally low glitch. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range 5.5 V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies to 50 MHz for IOVDD 5 V. The DAC8555 requires an external reference voltage to set the output range of each DAC channel. Also incorporated into the device is a power-on reset circuit which can be programmed to ensure that the DAC outputs power up at zero-scale or mid-scale and remain there until a valid write takes place. The device also has the capability to function in both binary and 2's complement mode. The DAC8555 provides a per channel power-down feature, accessed over the serial interface, that reduces the current consumption 200 nA per channel 5 V. The low-power consumption of this device in normal operation makes it ideally suited to portable batteryoperated equipment and other low-power applications. The power consumption 5 V, reducing �W in power-down mode. The DAC8555 is available a TSSOP-16 package with a specified operating temperature range to 105�C.APPLICATIONS
Portable Instrumentation Closed-Loop Servo-Control Process Control Data Acquisition Systems Programmable Attenuation PC Peripherals
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT DAC8555 PACKAGE LEAD TSSOP-16 PACKAGE DESIGNATOR (1) PW SPECIFICATION TEMPERATURE RANGE TO 105�C PACKAGE MARKING D8555 ORDERING NUMBER DAC8555IPW DAC8555IPWR TRANSPORT MEDIA, QUANTITY Tube, 90 Tape and Reel, 2000For the most current specifications and package information, refer to our web site at www.ti.com.
UNIT AVDD, IOVDD to GND Digital input voltage to GND VO(A) to VO(D) to GND Operating temperature range Storage temperature range Junction temperature range (TJ max) Power dissipation JA Thermal impedance JC Thermal impedance V to +AVDD V to +AVDD to 150�C (TJmax � TA)/JA 118�C/W 29�C/W
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.over operating free-air temperature range (unless otherwise noted)
PARAMETER STATIC PERFORMANCE (1) Resolution Relative accuracy Differential nonlinearity Zero-scale error Zero-scale error drift Full-scale error Gain error Gain temperature coefficient Power Supply Rejection Ratio (PSRR) OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time To �0.003% FSR, 500 pF Slew rate Capacitive load stability Code change glitch impulse Digital feedthrough DC crosstalk AC crosstalk DC output impedance Short-circuit current Power-up time AC PERFORMANCE SNR (1st 19 harmonics removed) THD SFDR SINAD REFERENCE INPUT Vref(H) Voltage Vref(L) Voltage Reference input current Reference input impedance Vref(L) < Vref(H) , AVDD - (Vref(H) + Vref(L)) 1.2 V Vref(L) < Vref(H) , AVDD - (Vref(H) + Vref(L)) 1.2 V Vref(L) = GND, Vref(H) = AVDD 5 V Vref(L) = GND, Vref(H) = AVDD 3 V Vref(L) < Vref(H) AVDD = 20 kHz, AVDD 5 V, FOUT = 1 kHz dB Full-scale swing on adjacent channel. AVDD 5 V, Vref V 1 kHz sine wave At mid-point input AVDD 5 V AVDD 3 V Coming out of power-down mode AVDD 5 V Coming out of power-down mode AVDD = RL LSB change around major carry VrefH V �s V/�s pF nV-s LSB 200 pF Measured by line passing through codes 485 and 64741, AVDD 5 V, Vref 4.99 V Measured by line passing through codes 485 and 64741, AVDD 5 V Measured by line passing through codes 485 and 64741 16-bit Monotonic Measured by line passing through codes 485 and Bits LSB mV �V/�C % of FSR % of FSR ppm of FSR/�C mV mV/V TEST CONDITIONS MIN TYP MAX UNIT
Linearity calculated using a reduced code range to 64741; output unloaded. Ensured by design and characterization, not production tested. 3