FEATURES Complete 12-Bit DAC No External Components Single +5 Volt Operation 1 mV/Bit with 4.095 V Full Scale True Voltage Output, 5 mA Drive Very Low Power �3 mW APPLICATIONS Digitally Controlled Calibration Servo Controls Process Control Equipment PC Peripherals
The is a complete, parallel input, 12-bit, voltage output DAC designed to operate from a single +5 volt supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost, and ease-of-use in +5 volt only systems. Included on the chip, in addition to the DAC, is a rail-to-rail amplifier, latch and reference. The reference (REFOUT) is trimmed to 2.5 volts, and the on-chip amplifier gains up the DAC output to 4.095 volts full scale. The user needs only supply a +5 volt supply. The DAC8562 is coded straight binary. The op amp output swings from to +4.095 volts for a one millivolt per bit resolution, and is capable of driving � 5 mA. Built using low temperature-coefficient silicon-chrome thin-film resistors, excellent linearity error over temperature has been achieved as shown below in the linearity error versus digital input code plot. Digital interface is parallel and high speed to interface to the fastest processors without wait states. The interface is very simple requiring only a single CE signal. An asynchronous CLR input sets the output to zero scale.
The DAC8562 is available in two different 20-pin packages, plastic DIP and SOL-20. Each part is fully specified for operation over to +85�C, and the full � 5% power supply range. For MIL-STD-883 applications, contact your local ADI sales office for the DAC8562/883 data sheet which specifies operation over the to +125�C temperature range.Figure 1. Linearity Error vs. Digital Input Code Plot
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STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale VoltageN INL DNL VZSE VFS TCVFS IOUT LDREG CL VREF IREF LNREJ LDREG VIL VIH IIL CIL tCEW tDS tDH tCLRW tS
Full-Scale Tempco ANALOG OUTPUT Output Current Load Regulation at Half Scale Capacitive Load REFERENCE OUTPUT Output Voltage Output Source Current Line Rejection Load Regulation LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance INTERFACE TIMING SPECIFICATIONS1, 4 Chip Enable Pulse Width Data Setup Data Hold Clear Pulse Width AC CHARACTERISTICS4 Voltage Output Settling Time6 Digital Feedthrough SUPPLY CHARACTERISTICS Positive Supply Current Power Dissipation Power Supply Sensitivity
Note 2 E Grade F Grade No Missing Codes Data = 000H Data FFFH3 E Grade F Grade Notes 3, 4 Data to , Data No Oscillation4
NOTES 1 All input control signals are specified with +5 V) and timed from a voltage level 2 1 LSB 1 mV for +4.095 V output range. 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground. 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice.DAC8562 WAFER TEST LIMITS unless otherwise noted)
STATIC PERFORMANCE Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage Reference Output Voltage LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current SUPPLY CHARACTERISTICS Positive Supply Current Power Dissipation Power Supply Sensitivity
NOTE 1 Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
VDD to DGND and AGND. +10 V Logic Inputs to DGND. �0.3 V, VDD 0.3 V VOUT to AGND. �0.3 V, VDD 0.3 V VREFOUT to AGND. �0.3 V, VDD 0.3 V AGND to DGND. �0.3 V, VDD IOUT Short Circuit to GND. 50 mA Package Power Dissipation. (TJ max � TA)/JA Thermal Resistance JA 20-Pin Plastic DIP Package (P). 74�C/W 20-Lead SOIC Package (S). 89�C/W Maximum Junction Temperature (TJ max). 150�C Operating Temperature Range. to +85�C Storage Temperature Range. to +150�C Lead Temperature (Soldering, 10 secs). +300�C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Table I. Control Logic Truth Table CE CLR DAC Register Function
Latched Transparent Latched with New Data Loaded with All Zeros Latched All Zeros
CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted.
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