DG183AP Datasheet

Hi-speed DRVRS W/dual SPST JFET Switches


Features, Applications

High-Speed Drivers and Dual DPST JFET Switches

D Constant On-Resistance Over Entire Analog Range D Low Leakage D Low Crosstalk D Break-Before-Make Switching D Rad Hardness

Low Distortion Eliminates Large Signal Errors High Precision Improved Channel Isolation Eliminates Inadvertent Shorting Between Channels D Fault Protection

Audio Switching Precision Switching Video Switching Video Routing Sample/Hold Aerospace

The DG183/184/185 are precision dual double-pole, single-throw (DPST) analog switches designed to provide accurate switching of video and audio signals. This series is ideally suited for applications requiring a constant on-resistance over the entire analog range. on-resistance include audio switching, video switching, and data acquisition.

The major difference in the devices is the on-resistance , DG185--75 W). Reduced errors are achieved through low leakage current (ID(on) < 2 nA). Applications which benefit from the flat JFET

To achieve fast and accurate switch performance, each device comprises four n-channel JFET transistors and a TTL compatible bipolar driver. In the on state, each switch conducts current equally well in either direction. In the off condition, the switches will block 20 V peak-to-peak, with feedthrough of less than at 10 MHz.

Refer to JAN38510 Information, Military Section *Common to Substrate and Case
0 1 Logic 0.8 V Logic 2.0 20V Document Number: D, 16-Jun-97 www.vishay.com S FaxBack 408-970-5600

V+ to V�. V+ to VD. VD to V�. VD to VD. VL to V�. VL to VIN. VL to VR. 8 V VIN to VR. VR to V�. VR to VIN. 2 V Current 200 mA Notes: a. All leads welded or soldered to PC Board. b. Derate 12 mW/_C above 75_C c. Derate 10 mW/_C above 75_C Current 30 mA Current (All Other Pins). 30 mA Storage Temperature. to 150_C Power Dissipationa 16-Pin Sidebrazeb. mW 14-Pin Flat Packc. 900 mW

Test Conditions Unless Specified Parameter Analog Switch

Analog Signal Rangee Drain-Source On-Resistance Source Off L k Leakage Current C t VANALOG rDS(on) = �10 mA, �20 V IS(off) �20 V ID(off) #7.5 V ID(on) IDSS 2 ms Pulse Duration Full Room Full Room Hot Room Hot Room Hot Room Hot Room Hot Room V W

Drain Off L k Leakage Current C t Channel On Leakage Current Saturation Drain Current

Input Current with Input Voltage High Input Current with Input Voltage Low IINH IINL VIN 5 V VIN 0 V Room Hot Full

Turn-On Time Turn-Off Time Source-Off Capacitance Drain-Off Capacitance Channel-On Capacitance Off Isolation ton toff CS(off) CD(off) CD(on) OIRR = 1 MHz = VS MHz, 75 W Room See Switching Time Test Circuit Room pF ns

Positive Supply Current Negative Supply Current Logic Supply Current Reference Supply Current IL IR VIN 5 V Room 4.5 1.5

Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function.



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