Monolithic Quad SPST, CMOS Analog Switches
The DG411 series monolithic CMOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole throw (SPST) analog switches, and TTL and CMOS compatible digital inputs. These switches feature lower analog ON resistance (<35) and faster switch time (tON < 175ns) compared to the or DG212. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG411 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40VP-P signals. Power supplies may be single-ended from +34V, or split from to �20V. The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a �15V analog input range. The switches in the DG411 and DG412 are identical, differing only in the polarity of the selection logic. Two of the switches in the DG413 (#1 and #4) use the logic of the DG211 and DG411 (i.e., a logic "0" turns the switch ON) and the other two switches use DG212 and DG412 positive logic. This permits independent control of turn-on and turn-off times for SPDT configurations, permitting "break-beforemake" or "make-before-break" operation with a minimum of external logic.Features
ON Resistance (Max). 35 Low Power Consumption (PD). <35�W Fast Switching Action - tON (Max). 175ns - tOFF (Max). 145ns Low Charge Injection Upgrade from DG211/DG212 TTL, CMOS Compatible Single or Split Supply OperationApplications
Audio Switching Battery Operated Systems Data Acquisition Hi-Rel Systems Sample and Hold Circuits Communication Systems Automatic Test Equipment
PART NUMBER DG413DJ DG413DY TEMP. RANGE (oC) to 85 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC 16 Ld PDIP 16 Ld SOIC PKG. NO. E16.3 M16.15
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright � Intersil Americas Inc. 2002. All Rights ReservedFour SPST Switches per Package Switches Shown for Logic "1" Input
PIN SYMBOL D1 S1 VGND D2 IN2 DESCRIPTION Logic Control for Switch 1. Drain (Output) Terminal for Switch 1. Source (Input) Terminal for Switch 1. Negative Power Supply Terminal. Ground Terminal (Logic Common). Source (Input) Terminal for Switch 4. Drain (Output) Terminal for Switch 4. Logic Control for Switch 4. Logic Control for Switch 3. Drain (Output) Terminal for Switch 3. Source (Input) Terminal for Switch 3. Logic Reference Voltage. Positive Power Supply Terminal (Substrate). Source (Input) Terminal for Switch 2. Drain (Output) Terminal for Switch 2. Logic Control for Switch 2.
V+ to V-. 44V GND to V-. 25V VL. (GND -0.3V) to (V+) +0.3V Digital Inputs, , VD (Note 1). (V-) -2V to (V+) or 30mA, Whichever Occurs First Continuous Current (Any Terminal). 30mA Peak Current, or D (Pulsed 1ms, 10% Duty Cycle Max). 100mA
Thermal Resistance (Typical, Note 2) JA (oC/W) PDIP Package. 90 SOIC Package. 110 Maximum Junction Temperature (Plastic Packages). 150oC Maximum Storage Temperature Range. to 150oC Maximum Lead Temperature (Soldering 10s). 300oC (SOIC - Lead Tips Only)
Voltage Range. �20V (Max) Temperature Range. to 85oC Input Low Voltage. 0.8V (Max) Input High Voltage. 2.4V (Min) Input Rise and Fall Time. 20ns
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals , or INX exceeding or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Test Conditions: = 5V, VIN 2.4V, 0.8V (Note 3), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) (NOTE 4) (NOTE 5) (NOTE 4) MIN TYP MAX UNITS
Break-Before-Make Time Delay Charge Injection, Q (Figure 3) OFF Isolation (Figure 5) Crosstalk (Channel-to-Channel), (Figure 4) Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current VIN Low, IIL Input Current VIN High, IIHVIN Under Test = 0.8V, All Others = 2.4V VIN Under Test = 2.4V, All Others = 0.8V
ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) = -13.5V Full 25 Full V