D Wide Bandwidth: 500 MHz D Very Low Crosstalk: @ 5 MHz D On-Board TTL-Compatible Latches with Readback D Optional Negative Supply D Low rDS(on): W D Single-Ended or Differential Operation D Latch-up Proof
Improved System Bandwidth Improved Channel Off-Isolation Simplified Logic Interfacing High-Speed Readback Allows Bipolar Signal Swings Reduced Insertion Loss Allows Differential Signal SwitchingAPPLICATIONS
D Wideband Signal Routing and Multiplexing D Video Switchers D ATE Systems D Infrared Imaging D Ultrasound ImagingDESCRIPTION
The is a digitally selectable 4-channel or dual 2-channel multiplexer. The 8-channel or dual 4-channel multiplexer. On-chip TTL-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. The low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and audio signal routing in channel selectors and crosspoint arrays. An optional negative supply pin allows the handling of bipolar signals without dc biasing. The DG534A/DG538A are built on a D/CMOS process that combines n-channel DMOS switching FETs with low-power CMOS control logic, drivers and latches. The low-capacitance DMOS FETs are connected in a "T" configuration to achieve extremely high levels of off isolation. Crosstalk is reduced at 5 MHz by including a ground line between adjacent signal paths. An epitaxial layer prevents latch-up.For more information refer to Vishay Siliconix applications note AN502.
1 X Note c Maintains previous state None (latches cleared) None SB4 SA1 and SB1 SA2 and SB2 SA3 and SB3 SA4 and SB4
Logic "0" = VAL 0.8 V Logic "1" = VAH Don't Care Notes: a. Connect DA and DB together externally for single-ended operation. b. With I/O high, An and EN pins become outputs and reflect latch contents. See timing diagrams for more detail. c. 8/4 can be either or "0" but should not change during these operations.