Routes Any Input to Any Output Wide Bandwidth: 300 MHz Low Crosstalk: @ 5 MHz Double Buffered TTL-Compatible Latches with Readback D Low rDS(on): W D Optional Negative Supply
Reduced Board Space Improved System Bandwidth Improved Channel Off-Isolation Simplified Logic Interfacing Allows Bipolar Signal Swings Reduced Insertion Loss High ReliabilityAPPLICATIONS
D Wideband Signal Routing and Multiplexing D High-End Video Systems D NTSC, PAL, SECAM Switchers D Digital Video Routing D ATE SystemsDESCRIPTION
The DG884 contains a matrix of 32 T-switches configured 8 4 crosspoint array. Any of the IN/OUT pins may be used as an input or output. Any of the IN pins may be switched to any or simultaneously to all OUT pins. Control data is loaded individually into four Next Event latches. When all Next Event latches have been programmed, data is transferred into the Current Event latches via a SALVO command. Current Event latch data readback is available to poll array status. Output disable capabilities make it possible to parallel multiple DG884s to form larger switch arrays. DIS outputs provide control signals used to place external buffers in a power saving mode. For additional information see applications note AN504 (FaxBack document number 70610).
The DG884 is built on a proprietary D/CMOS process that combines low capacitance switching DMOS FETs with low power CMOS control logic and drivers. The ground lines between adjacent signal input pins help to reduce crosstalk. The low on-resistance and low on-capacitance of the DG884 make it ideal for video and wideband signal routing.
Next Event latches loaded as defined in table below Next Event latches are transparent. Next Event data latched-in Data in all Next Event latches is simultaneously loaded into the Current Event latches, i.e., all new crosspoint addresses change simultaneously when SALVO goes low.
Current Event latches are transparent Current Event data latched-in Both next and Current Event latches are transparent A3 � High impedance A2, A3 become outputs and reflect the contents of the Current Event latches. B0, B1 determine which Current Event latches are being read All crosspoints opened (but data in Next Event latches is preserved)
to OUT1 Loaded to OUT1 Loaded to OUT1 Loaded to OUT1 Loaded to OUT1 Loaded to OUT1 Loaded to OUT1 Loaded to OUT1 Loaded Turn Off OUT1 Loaded to OUT2 Loaded to OUT2 Loaded to OUT2 Loaded to OUT2 Loaded to OUT2 Loaded to OUT2 Loaded to OUT2 Loaded to OUT2 Loaded Turn Off OUT2 Loaded to OUT3 Loaded to OUT3 Loaded to OUT3 Loaded to OUT3 Loaded to OUT3 Loaded to OUT3 Loaded to OUT3 Loaded to OUT3 Loaded Turn Off OUT3 Loaded to OUT4 Loaded to OUT4 Loaded to OUT4 Loaded to OUT4 Loaded to OUT4 Loaded to OUT4 Loaded to OUT4 Loaded to OUT4 Loaded Turn Off OUT4 Loaded
When = 0 Next Event latches are transparent. Each crosspoint is addressed individually, e.g., to connect to OUT1 thru OUT4 requires to be latched with each combination B0, B1. When = 0, all four DIS outputs pull low simultaneously.
V+ to GND. V+ to V�. V� to GND. VL to GND. V to (V+) 0.3 V Digital Inputs. (V�) V to (VL) or 20 mA, whichever occurs first VS, VD. (V�) V to (V�) or 20 mA, whichever occurs first CURRENT (any terminal) Continuous. 20 mA CURRENT or D) Pulsed ms 10% duty. 40 mA Storage Temperature (A Suffix). 150_C (D Suffix). to 125_C Notes: a. All leads soldered or welded to PC board. b. Derate 6 mW/_C above 75_C. c. Derate 16 mW/_C above 75_C. Operating Temperature (A Suffix). 125_C (D Suffix). to 85_C
Power Dissipation (Package)a 44-Pin Quad J Lead PLCCb. mW 44-Pin Quad J Lead Hermetic CLCCc. 1200 mW