EP1C4F324C8N Datasheet

Embedded - FPGAs (Field Programmable Gate Array)


The CycloneTM field programmable gate array family is based on a 1.5-V,0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logicelements (LEs) and up to 288 Kbits of RAM. With features like phaselockedloops (PLLs) for clocking and a dedicated double data rate (DDR)interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memoryrequirements, Cyclone devices are a cost-effective solution for data-pathapplications. Cyclone devices support various I/O standards, includingLVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,32-bit peripheral component interconnect (PCI), for interfacing with andsupporting ASSP and ASIC devices. Altera also offers new low-costserialconfiguration devices to configure Cyclone devices. EP1C4F324C8N Features • 2,910 to 20,060 LEs, see Table 1• Up to 294,912 RAM bits (36,864 bytes)• Supports configuration through low-cost serial configuration device• Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards• Support for 66-MHz, 32-bit PCI standard• Low speed (311 Mbps) LVDS I/O support• Up to two PLLs per device provide clock multiplication and phaseshifting• Up to eight global clock lines with six clock resources available perlogic array block (LAB) row• Support for external memory, including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM• Support for multiple intellectual property (IP) cores, includingAltera MegaCore functions and Altera Megafunctions PartnersProgram (AMPPSM) megafunctions


[{"Name":"Number of LABs/CLBs","Value":"400"},{"Name":"Number of Logic Elements/Cells","Value":"4000"},{"Name":"Total RAM Bits","Value":"78336"},{"Name":"Number of I /O","Value":"249"},{"Name":"Voltage - Supply","Value":"1.425 V ~ 1.575 V"},{"Name":"Operating Temperature","Value":"0°C ~ 85°C"},{"Name":"","Value":""},{"Name":"","Value":""},{"Name":"","Value":""},{"Name":"","Value":""}]

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