FDV302P Datasheet



This P-Channel logic level enhancement( FDV302P ) mode field effect transistor is produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for digital transistors. Since bias resistors are not required, this one P-channel FET can replace several digital transistors with different bias resistors such as the DTCx and DCDx series. FDV302P Features &bull;-25 V, -0.12 A continuous, -0.5 A Peak.- RDS(ON) = 13 W @ VGS= -2.7 V- RDS(ON) = 10 W @ VGS = -4.5 V.&bull;Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.5V.&bull;Gate-Source Zener for ESD ruggedness. >6kV Human Body Model&bull;Compact industry standard SOT-23 surface mount package.&bull;Replace many PNP digital transistors (DTCx and DCDx) with one DMOS FET.


[{"Name":"Drain-Source Breakdown Voltage:","Value":"- 25 V"},{"Name":"Gate-Source Breakdown Voltage:","Value":"- 8 V"},{"Name":"Continuous Drain Current:","Value":"0.12 A"},{"Name":"Resistance Drain-Source RDS (on):","Value":"13 Ohms"},{"Name":" Maximum Operating Temperature:","Value":"+ 150 C"},{"Name":" Fall Time:","Value":"8 ns"},{"Name":"Forward Transconductance gFS (Max / Min):","Value":"0.135 S"},{"Name":"Minimum Operating Temperature:","Value":"- 55 C"},{"Name":"Power Dissipation:","Value":"0.35 W"},{"Name":" Rise Time:","Value":"8 ns"}]

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