HomedatasheetGAL20V8B-15LPNI

GAL20V8B-15LPNI Datasheet

SPLD - Simple Programmable Logic Devices
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Description

The GAL20V8B-15LPNI , at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2 ) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures listed in the table of the macrocell description section. GAL20V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. GAL20V8B-15LPNI Features &bull; HIGH PERFORMANCE E2CMOS&reg; TECHNOLOGY 5 ns Maximum Propagation Delay Fmax = 166 MHz 4 ns Maximum from Clock Input to Data Output UltraMOS&reg; Advanced CMOS Technology&bull; 50% to 75% REDUCTION IN POWER FROM BIPOLAR 75mA Typ Icc on Low Power Device 45mA Typ Icc on Quarter Power Device&bull; ACTIVE PULL-UPS ON ALL PINS&bull; E2 CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells 100% Tested/100% Yields High Speed Electrical Erasure (<100ms) 20 Year Data Retention&bull; EIGHT OUTPUT LOGIC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity Also Emulates 24-pin PAL&reg; Devices with Full Function Fuse Map/Parametric Compatibility&bull; PRELOAD AND POWER-ON RESET OF ALL REGISTERS 100% Functional Testability GAL20V8B-15LPNI Applications &bull; DMA Control&bull; State Machine Control&bull; High Speed Graphics Processing&bull; Standard Logic Speed Upgrade
Features

Parameters

[{"Name":"Delay Time","Value":"15 ns"},{"Name":"Operating Supply Voltage","Value":"4.5 V to 5.5 V"},{"Name":"Supply Current","Value":"130 mA"},{"Name":"Maximum Operating Temperature","Value":"+ 85 C"},{"Name":"Minimum Operating Temperature","Value":"- 40 C"},{"Name":"Number of Product Terms per Macro","Value":"8"},{"Name":"Operating Temperature","Value":"- 40 C to + 85 C"},{"Name":"","Value":""},{"Name":"","Value":""},{"Name":"","Value":""}]

Manufacturer information

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