HomedatasheetIDT54FCT388915T70JB

IDT54FCT388915T70JB Datasheet

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)
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Description

DESCRIPTION:
The IDT54/74FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock.

FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
    (FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
    output, one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Output skew < 350ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from tPD max. spec)
• 32/–16mA drive at CMOS output voltage levels
• VCC = 3.3V ± 0.3V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC, LCC and SSOP packages

Features

Parameters


Manufacturer information

INTEGRATED DEVICE TECHNOLOGY
Warm Hint

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