IS42S32200E-6TLI Datasheet



IS42S32200E-6TLI ISSIs 64Mb Synchronous DRAM IS42S32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. IS42S32200E-6TLI Features • Clock frequency: 200, 166, 143 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Single 3.3V power supply• LVTTL interface• Programmable burst length:(1, 2, 4, 8, full page)• Programmable burst sequence: Sequential/Interleave• Self refresh modes• 4096 refresh cycles every 64 ms• Random column address every clock cycle• Programmable CAS latency (2, 3 clocks)• Burst read/write and burst read/single write operations capability• Burst termination by burst stop and precharge command• Available in Industrial temperature grade• Available in 400-mil 86-pin TSOP II and 90-ball BGA• Available in Lead free• Power Down and Deep Power Down Mode• Partial Array Self Refresh• Temperature Compensated Self Refresh• Output Driver Strength Selection


[{"Name":"Package / Case","Value":"TSOP-86"},{"Name":"Maximum Clock Frequency","Value":"166 MHz"},{"Name":"Supply Voltage - Max","Value":"3.6 V"},{"Name":"Supply Voltage - Min","Value":"3 V"},{"Name":"Access Time","Value":"8 ns, 5.5 ns"},{"Name":"Maximum Operating Current","Value":"160 mA"},{"Name":"Maximum Operating Temperature","Value":"+ 85 C"},{"Name":"Minimum Operating Temperature","Value":"- 40 C"},{"Name":"","Value":""},{"Name":"","Value":""}]

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