HomedatasheetIS45S32800D-7TLA1-TR

IS45S32800D-7TLA1-TR Datasheet

DRAM
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Description

ISSIs 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM( IS45S32800D / IS45S32800D-7TLA1-TR ) is organized in 2Meg x 32 bit x 4 Banks. IS45S32800D-7TLA1-TR Features • Clock frequency: 166, 143 MHz• Fully synchronous; all signals referenced to a positive clock edge• Internal bank for hiding row access/precharge• Single Power supply: 3.3V + 0.3V• LVTTL interface• Programmable burst length– (1, 2, 4, 8, full page)• Programmable burst sequence: Sequential/Interleave• Auto Refresh (CBR)• Self Refresh• 4096 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade)• Random column address every clock cycle
Features

Parameters

[{"Name":"Maximum Clock Frequency:","Value":"143 MHz"},{"Name":"Access Time:","Value":"6.5 ns, 5.4 ns"},{"Name":"Supply Voltage - Max:","Value":"3.6 V"},{"Name":"Supply Voltage - Min:","Value":"3 V"},{"Name":"Maximum Operating Current:","Value":"150 mA"},{"Name":"Maximum Operating Temperature:","Value":"+ 85 C"},{"Name":"Minimum Operating Temperature:","Value":"- 40 C"},{"Name":"","Value":""},{"Name":"","Value":""},{"Name":"","Value":""}]

Manufacturer information

RECTRON SEMICONDUCTOR
Warm Hint

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