MC74AC273DTR2G Datasheet

Flip Flops


The MC74AC273DTR2G /74ACT273 has eight edge-triggered D−type flip−flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip−flops simultaneously.The register is fully edge-triggered. The state of each D input, one setup time before the LOW−to−HIGH clock transition, is transferred to the corresponding flip−flop’s Q output. MC74AC273DTR2G Features • Ideal Buffer for MOS Microprocessor or Memory• Eight Edge-Triggered D Flip−Flops• Buffered Common Clock• Buffered, Asynchronous Master Reset• See MC74AC377 for Clock Enable Version• See MC74AC373 for Transparent Latch Version• See MC74AC374 for 3-State Version• Outputs Source/Sink 24 mA• MC74AC273DTR2G Has TTL Compatible Inputs• Pb−Free Packages are Available*


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