MC88915FN55 Datasheet

Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers


The MC88915FN55 Clock Driver utilizes phase&ndash;locked loop technology to lock its low skew outputs&rsquo; frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC&rsquo;s and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88915FN55 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple MC88915FN55&rsquo;s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards. MC88915FN55 Features &bull; Five Outputs (QO&ndash;Q4) with Output&ndash;Output Skew < 500 ps each being phase and frequency locked to the SYNC input&bull; The phase variation from part&ndash;to&ndash;part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the part&ndash;to&ndash;part skew)&bull; Input/Output phase&ndash;locked frequency ratios of 1:2, 1:1, and 2:1 are available&bull; Input frequency range from 5MHz &ndash; 2X_Q FMAX spec&bull; Additional outputs available at 2X and +2 the system &ldquo;Q&rdquo; frequency. Also a Q (180&deg; phase shift) output available&bull; All outputs have &plusmn;36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL&ndash;level compatible&bull; Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes


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