NDS332P Datasheet

P-Channel Logic Level Enhancement Mode Field Effect Transistor


These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance.These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. NDS332P Features &bull; -1A, -20 V, RDS(ON) = 0.41 W@ V GS = -2.7 V RDS(ON) = 0.3 W@ V GS = -4.5 V. &bull; Very low level gate drive requirements allowing direct operation in 3V circuits. V GS(th) < 1.0V. &bull; Proprietary package design using copper lead frame for superior thermal and electricalcapabilities. &bull; High density cell design for extremely low R DS(ON) . &bull; Exceptional on-resistance and maximum DC current capability. &bull; Compact industry standard SOT-23 surface Mount package.


[{"Name":"Drain to Source Voltage (Vdss) ","Value":"20V"},{"Name":"Current - Continuous Drain (Id) @ 25° C ","Value":"1A"},{"Name":"Rds On (Max) @ Id, Vgs ","Value":"300 mOhm @ 1.1A, 4.5V"},{"Name":"Vgs(th) (Max) @ Id ","Value":"1V @ 250μA"},{"Name":"Gate Charge (Qg) @ Vgs ","Value":"5nC @ 4.5V"},{"Name":"Input Capacitance (Ciss) @ Vds ","Value":"195pF @ 10V"},{"Name":"Power - Max ","Value":"460mW"},{"Name":"","Value":""},{"Name":"","Value":""},{"Name":"","Value":""}]

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