S80L188EC Datasheet



Unless specifically noted, all references to the 80C186EC apply to the 80C188EC, 80L186EC, and 80L188EC. References to pins that differ between the 80C186EC/80L186EC and the 80C188EC/80L188EC are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physically and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical.
The 80C186EC is one of the highest integration members of the 186 Integrated Processor Family. Two serial ports are provided for services such as interprocessor communication, diagnostics and mo dem interfacing. Four DMA channels allow for high speed data movement as well as support of the on board serial ports. A flexible chip select unit simplifies memory and peripheral interfacing. The three general purpose timer/counters can be used for a variety of time measurement and waveform generation tasks. A watchdog timer is provided to insure system integrity even in the most hostile of environments. Two 8259A compatible interrupt controllers handle internal interrupts, and, up to 57 external interrupt requests. A DRAM refresh unit and 24 multiplexed I/O ports round out the feature set of the 80C186EC.
The future set of the 80C186EC meets the needs of low-power, space-critical applications. Low-power applications benefit from the static design of the CPU and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a powerdown mode that halts operaton of the device and freezes the clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current.
The 80L186EC is the 3V version of the 80C186EC. The 80L186EC is functionally identical to the 80C186EC embedded processor. Current 80C186EC users can easily upgrade their designs to use the 80L186EC and benefit from the reduced power consumption inherent in 3V operation.

■ Fully Static Operation
■ True CMOS Inputs and Outputs
■ Integrated Feature Set:
   — Low-Power, Static, Enhanced 8086 CPU Core
   — Two Independent DMA Supported UARTs, each with an Integral Baud Rate Generator
   — Four Independent DMA Channels
   — 22 Multiplexed I/O Port Pins
   — Two 8259A Compatible Programmable Interrupt Controllers
   — Three Programmable 16-Bit Timer/Counters
   — 32-Bit Watchdog Timer
   — Ten Programmable Chip Selects with Integral Wait-State Generator
   — Memory Refresh Control Unit
   — Power Management Unit
   — On-Chip Oscillator
   — System Level Testing Support (ONCE Mode)
■ Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I/O
■ Low-Power Operating Modes:
   — Idle Mode Freezes CPU Clocks but Keeps Peripherals Active
   — Powerdown Mode Freezes All Internal Clocks
   — Powersave Mode Divides All Clocks by Programmable Prescalar
■ Available in Extended Temperature Range (-40°C to +85°C)
■ Supports 80C187 Numerics Processor Extension (80C186EC only)
■ Package Types:
   — 100-Pin EIAJ Quad Flat Pack (QFP)
   — 100-Pin Plastic Quad Flat Pack (PQFP)
   — 100-Pin Shrink Quad Flat Pack (SQFP)
■ Speed Versions Available (5V):
   — 25 MHz (80C186EC25/80C188EC25)
   — 20 MHz (80C186EC20/80C188EC20)
   — 13 MHz (80C186EC13/80C188EC13)
■ Speed Version Available (3V):
   — 16 MHz (80L186EC16/80L188EC16)
   — 13 MHz (80L186EC13/80L188EC13)



Manufacturer information


Intel and Altera announced on June 1, 2015, that they had entered into a definitive agreement under which Intel would acquire Altera. The transaction closed December 28, 2015. The acquisition couples Intel’s leading-edge products and manufacturing process with Altera’s leading field-programmable gate array (FPGA) technology. The combination enables new classes of products that meet customer needs in the data center and Internet of Things (IoT) market segments.

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