SN65LVDS94DGG Datasheet

LVDS Interface IC


The SN65LVDS94DGG LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7&times; clock synthesizer,and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate. SN65LVDS94DGG Features &bull; 4:28 Data Channel Expansion at up to 1.820 Gigabits per Second Throughput&bull; Suited for Point-to-Point Subsystem Communication With Very Low EMI&bull; 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out&bull; Operates From a Single 3.3-V Supply and 250 mW (Typ)&bull; 5-V Tolerant SHTDN Input&bull; Rising Clock Edge Triggered Outputs&bull; Bus Pins Tolerate 4-kV HBM ESD&bull; Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch&bull; Consumes <1 mW When Disabled&bull; Wide Phase-Lock Input Frequency Range 20 MHz to 65 MHz&bull; No External Components Required for PLL&bull; Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard&bull; ndustrial Temperature Qualified TA = &ndash;40&deg;C to 85&deg;C&bull; Replacement for the DS90CR286


[{"Name":"Number of Drivers","Value":"28"},{"Name":"Number of Receivers","Value":"4"},{"Name":"Data Rate","Value":"1904 Mbps"},{"Name":"Operating Supply Voltage","Value":"3.3 V"},{"Name":"Maximum Power Dissipation","Value":"1377 mW"},{"Name":"Maximum Operating Temperature ","Value":"+ 85 C "},{"Name":"Package / Case ","Value":"TSSOP-56"},{"Name":"Packaging","Value":"Tube "}]

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