SN74AHC595DBR Datasheet

Counter Shift Registers


The SN74AHC595DBR devices contain an 8-bit serial-in,parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs, except QH′, are in the high-impedance state. SN74AHC595DBR Features • Operating Range 2-V to 5.5-V VCC• 8-Bit Serial-In, Parallel-Out Shift• Shift Register Has Direct Clear• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II• ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)


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