SN74ALS74ADG4 Datasheet

Flip Flops


These SN74ALS74ADG4 is devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. SN74ALS74ADG4 Features • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs


[{"Name":"Number of Circuits","Value":"2"},{"Name":"Logic Family ","Value":"74ALS "},{"Name":"Logic Type","Value":"D-Type Flip-Flop"},{"Name":"Polarity ","Value":"Inverting/Non-Inverting "},{"Name":"Input Type","Value":"Single-Ended"},{"Name":"Output Type","Value":"Differential"},{"Name":"Propagation Delay Time ","Value":"18 ns "},{"Name":"High Level Output Current ","Value":"- 0.4 mA "},{"Name":"Low Level Output Current ","Value":"8 mA "},{"Name":"Packaging","Value":"Tube "}]

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