TSB41AB2 Datasheet

Interface - Drivers, Receivers, Transceivers


The TSB41AB2 provides the digital and analog transceiver functions needed to implement a two-port node ina cable-based IEEE 1394 network. The cable ports incorporate two differential line transceivers. Thetransceivers include circuitry to monitor the line conditions as needed for determining connection status, forinitialization and arbitration, and for packet reception and transmission. The TSB41AB2 is designed to interfacewith a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31,TSB12LV41, TSB12LV42, or TSB12LV01A.The TSB41AB2 requires only an external 24.576-MHz crystal as a reference. An external clock may be providedinstead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates therequired 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signalsused to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signalis supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of thereceived data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operationof the PLL.The TSB41AB2 supports an optional isolation barrier between itself and its LLC. When the ISO input terminalis tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiatinglogic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformergalvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and inIEEE 1394a-2000 (section5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation, the ISO terminalon the PHY must be high.Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths(depending on the requested transmission speed) and are latched internally in the TSB41AB2 insynchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmittedat 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as theoutbound data-strobe information stream. During transmission, the encoded data information is transmitteddifferentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on theTPA cable pair(s).During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receiversfor that port are enabled. The encoded data information is received on the TPA cable pair, and the encodedstrobe information is received on the TPB cable pair. The received data-strobe information is decoded to recoverthe receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallelstreams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clockand sent to the associated LLC.Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states duringinitialization and arbitration. The outputs of these comparators are used by the internal logo determine thearbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of thiscommon-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of theremotely supplied twisted-pair bias voltage.The TSB41AB2 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This biasvoltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. Thisbias voltage source must be stabilized by an external filter capacitor of 1 μF. TPBIAS is close to VDD when anactive port is not connected to another node.


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