W971GG6JB-3 Datasheet



The W971GG6JB is a 1G bits DDR2 SDRAM, organized as 8,388,608 words 8 banks 16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications. W971GG6JB is sorted into the following grade parts: -18, -25, 25L, 25I, 25A, 25K, -3 and -3A. The -18 grade parts is compliant to the DDR2-1066 (6-6-6) specification. The -25/25L/25I/25A/25K grade parts are  compliant  to  the  DDR2-800  (5-5-5)  specification  (the  25L  grade  parts  is  guaranteed  to  support IDD2P = 7 mA and IDD6 = 4 mA at commercial temperature, the 25I industrial grade parts is guaranteed to  support  -40°C  ≤  TCASE  ≤  95°C).  The  -3/-3A  grade  parts  is  compliant  to  the  DDR2-667  (5-5-5) specification.

Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver  impedance  adjustment  (OCD)  and  On-Die-Termination  (ODT)  for  better  signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant



Manufacturer information

Warm Hint

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