HomedatasheetXC3S200

XC3S200 Datasheet

Platform Flash In-System Programmable Configuration PROMS
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Description

The Spartan™-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to five million system gates. The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from state-of-the-art Virtex™-II technology. These Spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment. The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs. XC3S200 Features • Revolutionary 90-nanometer process technology• Very low cost, high-performance logic solution for high-volume, consumer-oriented applications - Densities as high as 74,880 logic cells - 326 MHz system clock rate - Three power rails: for core (1.2V), I/Os (1.2V to 3.3V), and auxiliary purposes (2.5V)• SelectIO™ signaling - Up to 784 I/O pins - 622 Mb/s data transfer rate per I/O - Seventeen single-ended signal standards - Seven differential signal standards including LVDS - Termination by Digitally Controlled Impedance - Signal swing ranging from 1.14V to 3.45V - Double Data Rate (DDR) support• Logic resources - Abundant logic cells with shift register capability - Wide multiplexers - Fast look-ahead carry logic - Dedicated 18 x 18 multipliers - JTAG logic compatible with IEEE 1149.1/1532 specifications• SelectRAM™ hierarchical memory - Up to 1,872 Kbits of total block RAM - Up to 520 Kbits of total distributed RAM• Digital Clock Manager (up to four DCMs) - Clock skew elimination - Frequency synthesis - High resolution phase shifting• Eight global clock lines and abundant routing• Fully supported by Xilinx ISE development system - Synthesis, mapping, placement and routing• MicroBlaze processor, PCI, and other cores
Features

Parameters

[{"Name":"Maximum Supply voltage relative to GND VCC","Value":"–0.5 to +7.0 V"},{"Name":"Maximum Supply voltage relative to GND VPP","Value":"–0.5 to +12.5 V"},{"Name":"Maximum Input voltage relative to GND VIN ","Value":"–0.5 to VCC +0.5 V"},{"Name":"Maximum Voltage applied to High-Z output VTS","Value":"–0.5 to VCC +0.5 V"},{"Name":"Maximum Storage temperature (ambient) TSTG","Value":"–65 to +150 °C"},{"Name":"Maximum Junction temperature TJ","Value":"+125 °C"},{"Name":"","Value":""},{"Name":"","Value":""},{"Name":"","Value":""},{"Name":"","Value":""}]

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