This product is Sigma-Delta Digital-To-Analog Converter for High grade Digital Audio Applications. The product contains Serial-to-Parallel Interface Converter and Compensation Filter, Digital Volume Attenuator by the Mode Interface, De-Emphasis Filter, FIR filter, Sinc Filter, Digital Sigma-Delta Modulator, Analog Postfilter, AIF (AntiImage-Filter). The normal input and output channels provides 95dB SNR (Signal to Noise Ratio) over in band (20kHz : Sampling Rate = 44.1KHz). The product employs the 1bit 4th-order Sigma-Delta architecture with 16bit resolution, over sampling of 64X. And Analog Postfilter with low clock sensitivity and Linear phase, filters the Shaping-Nosie and outputs Analog voltage with high resolution. An on-chip reference voltage is included to allow single supply operations.FEATURES
16/20/24bit Sigma-Delta Digital-to-Analog Converter Sampling Frequency Rate 32/44.1/48kHz Input Rate 2Fs by Normal Mode/Double Mode Selection On-Chip Compensation Filter On-Chip 4 times Oversampling Digital Filter On-Chip Analog Postfilter Filtered Line-Level Outputs, Linear Phase Filtering On-Chip Voltage Reference Low Clock Jitter Sensitivity 96dB SNR L/R Independent Digital Soft Attenuation On-Chip De-Emphasis Filter (32/44.1/48kHz) Zero Input Detection Mute Soft Mute Control Mono/Stereo Setting Single / 3.3V(Digital/Analog) Power SupplyAPPLICATIONS
CD Player, CD-ROM, MP3 Player, Video-CD, Mini-Disk, DVD etc.
(I)* : Input (O)* : Output (B)* : Bidirection
VCOMML(I)* VCOMCL(I)* VCOML(I)* VREFML(I)* VREFPL(I)* VHALF(O)* VREFIN(I)* VREF(O)* VREFPR(I)* VREFMR(I)* VCOMR(I)* VCOMCR(I)* VCOMMR(I)*
Ver 4.1 (Feb. 2002) This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice.BISTONP SDIAG SERRORB TSEL OFS64 ODSL ODSR IFS64 IADSL IADSR IFEF(B)*
External Inputs MSCK BCK LRCK SDATA External AOUTL AOUTR VHALF VREF VREFIN This pin must be connected to VHALF PAD VCOML VCOMCL VCOMML Each ports must be VREFPL connected to VREF VCOMR PAD VCOMCR VCOMMR VREFPR Each ports must be VREFML connected to VREFMR AVSS33A PAD IREF SDIAG SERRORB OFS64 ODSL ODSR
MUX_SEL MODE MCKDEM MLDFS0 DN IIS IFS MUTEL ZDENL RSTB PDL IDNUM<3:0> ZDENH BISTONP TSEL IFS64 IADSL IADSR
These are test pins for internal blocks of the core. So you don't need the internal test mode. Make the test control pins disable ('L') state and Output and bidirectional pins leave floating.