dac1243x_sr Datasheet

Mixed Signal Cores->0.25um


Features, Applications

This core is a CMOS single-channel 10bit 30MSPS D/A converter for general & video applications. The dac1243x_sr core is implemented in the Samsung 0.25um 2.5V CMOS process. Digital inputs are coded with straight binary. This DAC includes independent power down control and the ability to sense output load. An external(optional) or internal 0.7V reference voltage(VBIAS) and a single external resister define the full-scale output current together. It uses the two architecture of current-segment and binary-weighted.


Maximum conversion rate 40MSPS +2.5V CMOS monolithic construction �0.75LSB differential linearity (typical) �1.0LSB integral linearity (typical) External or internal voltage reference (Including Band Gap Reference Block) Single Channel DAC 10-Bit parallel Straight Binary Digital input DAC auto-load detection circuitry Temperature ~ 70�C Just analog switch power_down enable


High Definition Television(HDTV) High Resolution Color Graphics Hard Disk Driver (HDD) CAE/CAD/CAM Image Processing Instrumentation

Segmented MSBs D1[9:0] PDAC Digital Decode Segmented MSBs

Ver 1.2 (Sep. 2000) This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice.

Name PDAC CLK PRE I/O Type DI I/O Pad piar50_abb picc_abb piar50_abb Pin Description Power down control just for Analog Switch Block When activated(high) all current switches are disabled. DAC master clock. Input data is latched into the DACs on the rising edge of CLK. Control strobe for the DAC auto-load detection comparator. When PRE transitions high-to-low, the auto-load detect circuit evaluates its analog input. Appropriate settling time must be allowed before the comparator output (DTOUT) is used. When not used, PRE should be left high. 10-bit straight binary, parallel digital input Selection control for this DAC output as an input of auto load-detection function. Enable of load detection for the DAC is SEL=Low. Power down control for Bandgap and all blocks. A high level disables all analog switches and digital blocks plus the band gap reference regardless of the states of PDAC Comparator output for detection of resistive load at DAC output. A low at the detect output indicates that the output voltage of the current selected DAC is above 0.53V and therefore that no load is attached. Internal DAC compensation node. Connect external 0.1uF cap to VDD25AA1. External resistor from this node to VSS25AA1 defines the full scale output current for the DACs. External reference voltage output. Analog Power (2 pads for this node is recommended.) Analog Ground (2 pads for this node is recommended) Digital Power Digital Ground Substrate Bias(the same with ground level) Analog Current Output


AO: Analog Output DO: Digital Output AB: Analog Bidirectional DB: Digital Bidirectional AP: Analog Power DP: Digital Power AG: Analog Ground DG: Digital Ground



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