dac1350x Datasheet

Mixed Signal Cores->0.18um


Features, Applications

This core is a CMOS quad-channel 10bit 75MSPS D/A converter for general & video applications. The dac1350x core is implemented in the Samsung 0.18um 3.3V CMOS process. Digital inputs are coded as straight binary. Each dac channel includes dependent power down control and the ability to sense output load. An external(optional) or internal 0.7V reference voltage (VREFOUT) and a single external resister define the fullscale output current together. It uses the two architecture of current-segment and binary-weighted.


Maximum conversion rate 75MSPS +3.3V CMOS monolithic construction �1 LSB differential linearity (max) �2 LSB integral linearity (max) External or internal voltage reference (Including Band Gap Reference Block) 10-Bit parallel digital input DAC auto-load detection circuitry Temperature ~ 70�C Each channel Power_Down Power Dump Mode

High Definition Television(HDTV) High Resolution Color Graphics Image Processing
CLK DTOUT DACPRE DLDSEL[1:0] BGPD Band gap reference generator

Ver 1.8 (May. 2002) No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any notice.

Pin Name INPUTS DACLP[3:0] DI picc_abb Individual DAC power down control. When activated(high), the corresponding DAC is disabled. Low power current dumping mode control for each DAC. When selected (high enables low power mode) the corresponding DAC will run at reduced power with a slight loss in performance. DAC master clock. Input data is sampled with the rising edge of CLK. Control strobe for the DAC auto-load detection comparator. When DACPRE transitions high-to-low, the auto-load detect circuit evaluates its selected input. Appropriate settling time must be allowed before the comparator output (DTOUT) is used. When not used, DACPRE should be left high. 10-bit straight binary digital input for each DAC channel. I/O Type I/O Pad Pin Description

Power down control for Bandgap and all quad DACs. A high level disables all quad DACs plus the bandgap reference regardless of the states of PDDAC0,PDDAC1,PDDAC2,PDDAC3 Selection control for external DAC auto-load detection. Enable of load for IOUT0 is selected is DLDSEL[1:0]="11" Comparator output for detection of resistive load at DAC output. A low at the detect output indicates that the output voltage of the selected channel is above 0.53V and therefore that no load is attached. Analog Current Output for each of the four DACs

Connect external 0.1uF cap to AVDD33A. External resistor from this node to AVSS33A defines the full scale output current for the DACs. Connect external 0.1uF cap and 100ohm resistor to AVDD33A. internal / external voltage reference output



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